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参数资料
| 型号： | AD5251BRU10 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14 |
| 封装： | MO-153AB-1, TSSOP-14 |
| 文件页数： | 15/28页 |
| 文件大小： | 859K |
| 代理商： | AD5251BRU10 |
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AD5251/AD5252
I
2
C COMPATIBLE 2-WIRE SERIAL BUS
Rev.0 | Page 15 of 28
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
SCL
ACK. BY
AD525x
ACK. BY
AD525x
ACK. BY
AD525x
FRAME 1
DATA BYTE
STOP BY
MASTER
0
START BY
MASTER
0
1
1
0
1
1
AD1 AD0 R/W
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
9
1
9
1
9
Figure 13. General I
2
C Write Pattern
0
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
SCL
ACK. BY
AD525x
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER
0
1
1
0
1
1
AD1 AD0
D7
D6
D5
D4
D3
D2
D1
D0
9
1
9
R/W
Figure 14. General I
2
C Read Pattern
The first byte of the AD5251/AD5252 is a slave address byte
(see Figure 12 and Figure 13). It has a 7-bit slave address and an
R/W bit. The 5 MSBs of the slave address are 01011, and the
following 2 LSBs are determined by the states of the AD1 and
AD0 pins. AD1 and AD0 allow the user to place up to four
parts on one bus.
AD5251/AD5252 can be controlled via an I
2
C compatible serial
bus, and are connected to this bus as slave devices. The 2-wire
I
2
C serial bus protocol (see Figure 13 and Figure 14) follows:
1.
The master initiates a data transfer by establishing a start
condition, such that SDA goes from high to low while SCL
is high (see Figure 13). The following byte is the slave
address byte, which consists of the 5 MSBs of a slave
address defined as 01011. The next two bits are AD1 and
AD0, I
their AD1 and AD0 bits, four parts can be addressed on
the same bus. The last LSB, the R/W bit, determines
whether data is read from or written to the slave device.
SCL (see Figure 13).
2
C device address bits. Depending on the states of
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
2.
In the write mode (except when restoring EEMEM to the
RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/REG. MSB = 1 enables CMD, the command
instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/RDAC,
is true only when MSB = 0 or is in general writing mode.
EE enables the EEMEM register and REG enables the
RDAC register. The 5 LSBs, A4 to A0, designate the
addresses of the EEMEM and RDAC registers, (see Figure
7 and Figure 8). When MSB = 1 or when in CMD mode,
the four bits following MSB are C3 to C1, which
correspond to 12 predefined EEMEM controls and quick
commands; there also are four factory reserved commands.
The 3 LSBs—A2, A1, and A0—are four addresses, but only
001 and 011 are used for RDAC1 and RDAC3, respectively
(see Figure 10). After acknowledging the instruction byte,
the last byte in the write mode is the data byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
3.
In current read mode, the RDAC0 data byte immediately
follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on (there is a slight difference in write mode, where
the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 14). Another reading method, random
read method, is shown in Figure 10.
4.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop
condition (see Figure 13). In read mode, the master issues a
no acknowledge for the ninth clock pulse, i.e., the SDA line
remains high. The master then brings the SDA line low
before the 10
th
clock pulse, which goes high to establish a
stop condition (see Figure 14).
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| AD5251BRU100 | 制造商:Analog Devices 功能描述:Digital Potentiometer 64POS 100KOhm Dual 14-Pin TSSOP 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 64POS 100KOHM DUAL 14TSSOP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:6-BIT I2C EEMEM DIGIPOT - Bulk 制造商:Analog Devices 功能描述:DIGIPOT 6BIT I2C MEMORY 100K 5251 |
| AD5251BRU100-RL7 | 功能描述:IC DCP DUAL 100K 64POS 14TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5251BRU10-RL7 | 功能描述:IC DCP DUAL 10K 64POS 14TSSOP TR RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5251BRU1-RL7 | 功能描述:IC DCP DUAL 1K 64POS 14TSSOP T/R RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
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