参数资料
型号: AD5251BRU50-RL7
厂商: ANALOG DEVICES INC
元件分类: 数字电位计
英文描述: 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23
中文描述: DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14
封装: MO-153AB-1, TSSOP-14
文件页数: 21/28页
文件大小: 859K
代理商: AD5251BRU50-RL7
AD5251/AD5252
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFETs cross
conduction current when the driving signals are lower than
V
DD
. SCL and WP have ESD protection diodes, as shown in
Figure 35 and Figure 36.
Rev. 0 | Page 21 of 28
WP can be permanently tied to V
DD
without a pull-up resistor if
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write-protect. In
applications where the device is not being programmed on a
frequent basis, this allows the part to default to write-protect
after any one-time factory programming or field calibration
without the use of an on board pull-down resistor. Because
there are protection diodes on all these inputs, their signal levels
must not be greater than V
DD
to prevent forward biasing of the
diodes.
0
GND
SCL
V
DD
Figure 35. SCL Digital Input
0
GND
INPUTS
WP
V
DD
Figure 36. Equivalent WP Digital Input
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252s to be
operated on one I
2
C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I
2
C programming, each
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1
AD0
0
0
0
1
1
0
1
1
Device Addressed
U1
U2
U3
U4
0
V
DD
R
P
R
P
+5V
V
DD
V
DD
U1
AD0
AD1
SDA SCL
MASTER
U2
AD0
AD1
SDA SCL
U3
AD0
AD1
SDA SCL
U4
AD0
AD1
SDA
SDA
SCL
SCL
Figure 37. Multiple AD5251/AD5252s on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundary of the
terminal operating voltages. Positive signals present on
Terminal A, B, or W that exceed V
DD
are clamped by the
forward biased diode. Similarly, negative signals on Terminal A,
B, or W that are more negative than V
SS
are also clamped (see
Figure 38). In practice, users should not operate V
AB
, V
WA
, and
V
WB
to be higher than the voltage across V
DD
to V
SS
, but V
AB
,
V
WA
, and V
WB
have no polarity constraint.
V
SS
V
DD
A
W
B
0
Figure 38. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power-on V
DD
/V
SS
before applying any voltage to Terminals A,
B, and W. Otherwise, the diodes are forward-biased such that
V
DD
/V
SS
are powered unintentionally and may affect the rest of
the user’s circuit. Similarly, V
DD
/V
SS
should be powered down
last. The ideal power-up sequence is in the following order:
GND, V
DD
, V
SS
, digital inputs, and V
A
/V
B
/V
W
. The order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important, as
long as they are powered after V
DD
/V
SS
.
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