参数资料
型号: AD5254BRU100
厂商: ANALOG DEVICES INC
元件分类: 数字电位计
英文描述: Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers
中文描述: QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20
封装: MO-153AC, TSSOP-20
文件页数: 7/28页
文件大小: 834K
代理商: AD5254BRU100
AD5253/AD5254
INTERFACE TIMING CHARACTERISTICS (ALL PARTS)
Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified
with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both
V
DD
= 3 V and 5 V. When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the
I
2
C interface at these pins conducts current of about 0.8 mA at V
DD
= 5.5 V and 0.2 mA at V
DD
= 2.7 V.
Table 3.
Parameter
Symbol
Conditions
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated
t
LOW
Low Period of SCL Clock
t
3
t
HIGH
High Period of SCL Clock
t
4
t
SU;STA
Setup Time for START Condition
t
5
t
HD;DAT
Data Hold Time
t
6
t
SU;DAT
Data Setup Time
t
7
t
F
Fall Time of Both SDA and SCL Signals
t
8
t
R
Rise Time of Both SDA and SCL Signals
t
9
t
SU;STO
Setup Time for STOP Condition
t
10
EEMEM Data Storing Time
t
EEMEM_STORE
EEMEM Data Restoring Time at Power On
9
t
EEMEM_RESTORE1
V
DD
rise time dependent. Measure without
decoupling capacitors at V
DD
and V
SS
.
EEMEM Data Restoring Time upon Restore
Command or RESET Operation
9
EEMEM Data Rewritable Time
10
t
EEMEM_REWRITE
FLASH/EE MEMORY RELIABILITY
Endurance
11
Data Retention
12
Rev. 0 | Page 7 of 28
Min
1.3
0.6
Typ
1
Max
400
Unit
kHz
μs
μs
1.3
0.6
0.6
0
100
0.6
26
300
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
t
EEMEM_RESTORE2
V
DD
= 5 V
300
μs
100
540
100
μs
kCycles
Years
1
Typical values represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 k
version at V
DD
= 2.7V, I
W
= V
DD
/R for both V
DD
= 3 V or V
DD
= 5 V.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4
Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
cmd 0 NOP should be activated after cmd 1 in order to minimize I
DD_RESTORE
current consumption.
7
P
DISS
is calculated from (I
DD
× V
DD
= 5 V).
8
All dynamic characteristics use V
DD
= 5 V.
9
During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time.
10
Delay time after power-on or RESET before new EEMEM data to be written.
11
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
12
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
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