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参数资料
| 型号： | AD5255 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 18 Bit, 1.25MSPS Single Channel Delta-Sigma ADC Single 64-HTQFP -40 to 85 |
| 中文描述： | 3通道数字电位器的非易失性存储器 |
| 文件页数： | 15/20页 |
| 文件大小： | 626K |
| 代理商： | AD5255 |
AD5255
THEORY OF OPERATION
The AD5255 digital potentiometer operates as a true variable
resistor. The RDAC register contents determine the resistor
wiper position. The RDAC register acts like a scratch-pad
register, allowing unlimited resistance setting changes. RDAC
register contents are changed using the AD5255’s serial I
2
C
interface. See the RDAC I2C Interface section for the format of
the data words and commands to program the RDAC registers.
Rev. 0 | Page 15 of 20
Each RDAC register has a corresponding EEPROM memory
location, which provides nonvolatile storage of resistor wiper
position settings. The AD5255 provides commands to store the
RDAC register contents to their respective EEPROM memory
locations. During subsequent power-on sequences, the RDAC
registers are automatically loaded with the stored values.
Saving data from an RDAC register to EEPROM memory takes
approximately 25 ms and consumes 35 mA.
In addition to moving data between RDAC registers and
EEPROM memory, the AD5255 provides other shortcut
commands.
Table 9. AD5255 Shortcut Commands
No.
Function
1
Restore EEPROM setting to RDAC
1
2.
Store RDAC register contents to EEPROM
2
3
Decrement RDAC 6 dB (shift data bits right)
4
Decrement all RDACs 6 dB (shift all data bits right)
5
Decrement RDAC 1 step
6
Decrement all RDACs 1 step
7
Reset EEPROM setting to RDAC
2
8
Increment RDAC 6 dB (shift data bits left)
9
Increment all RDACs 6 dB (shift all data bits left)
10
Increment RDAC 1 step
11
Increment all RDACs 1 step
__________________________
1
Command leaves the device in the EEPROM read power state. Issue the NOP
command to return the device to the idle state.
2
Command requires acknowledge polling after execution.
LINEAR INCREMENT AND DECREMENT
COMMANDS
The increment and decrement commands (Commands 10, 11,
5, and 6) are useful for linear step adjustment applications.
These commands simplify microcontroller software coding by
allowing the controller to send only an increment or decrement
command to the AD5255. The adjustment can be directed to an
individual RDAC or to all three RDACs.
LOGARITHMIC TAPER MODE ADJUSTMENT
(
±
6 dB/STEP)
The AD5255 accommodates logarithmic taper adjustment of
the RDAC wiper position(s) by shifting the register contents
left/right for increment/decrement operations. Commands 8, 9,
3, and 4 are used to logarithmically increment or decrement the
wiper positions individually or change all three channel settings
at the same time.
Incrementing the wiper position by +6 dB doubles the RDAC
register value, while decrementing by 6 dB halves it. Internally,
the AD5255 uses a shift register to shift the bits left and right to
achieve a logarithmic increment or decrement.
Nonideal ±6 dB step adjustment occurs under certain conditions.
Table 10 illustrates how the shifting function affects the data
bits of an individual RDAC. Each line going down the table
represents a successive shift operation. Note that the left-shift
commands (Commands 10 and 11) were modified such that if
the data in the RDAC register equals 0 and the data is shifted,
the RDAC register is set to Code 1. Similarly, if the data in the
RDAC register is greater than or equal to midscale and the data
is left shifted, the data in the RDAC register is automatically set
to full-scale. This makes the left-shift function as close as possible
to a logarithmic adjustment.
The right-shift commands (Commands 3 and 4) are ideal only
if the LSB is a 0 (ideal logarithmic = no error). If the LSB is 1,
the right-shift function generates a linear half LSB error.
Table 10. RDAC Register Contents after
±
6 dB Step Adjustments
Left Shift (+6 dB/step)
0 0000 0000
0 0000 0001
0 0000 0010
0 0000 0100
0 0000 1000
0 0001 0000
0 0010 0000
0 0100 0000
0 1000 0000
1 0000 0000
1 1111 1111
1 1111 1111
Right Shift (6 dB/step)
1 1111 1111
0 1111 1111
0 0111 1111
0 0011 1111
0 0001 1111
0 0000 1111
0 0000 0111
0 0000 0011
0 0000 0001
0 0000 0000
0 0000 0000
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift command (Commands 3 and 4) execution contains
an error only for odd numbers of bits. Even numbers of bits are
ideal. Figure 26 shows a plot of Log_Error, that is, 20 ×
Log10(error/code), for the AD5255.
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相关代理商/技术参数 |
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| AD5255BRU25 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 512POS 25KOHM TRIPLE 24TSSOP - Rail/Tube |
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| AD5255BRU25-RL7 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 512POS 25KOHM TRIPLE 24TSSOP - Tape and Reel |
| AD5255BRUZ25 | 制造商:Analog Devices 功能描述:Digital Potentiometer 512POS 25KOhm Triple 24-Pin TSSOP 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 512POS 25KOHM TRIPLE 24TSSOP - Rail/Tube 制造商:Analog Devices 功能描述:DIGIPOT I2C NV MEMORY 5K SMD 5255 |
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