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| 型号： | AD5259 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 18 Bit, 1.25MSPS Single Channel Delta-Sigma ADC Single with FIFO 64-HTQFP -40 to 105 |
| 中文描述： | 非易失，I2C兼容256级，数字电位器 |
| 文件页数： | 16/24页 |
| 文件大小： | 1039K |
| 代理商： | AD5259 |
AD5259
I
2
C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control
registers for the AD5259 all refer to the device addresses listed
in Table 5; the mode/condition reference key (S, P, SA, MA,
NA, W, R, and X) is listed below.
S
= Start Condition
Rev. A | Page 16 of 24
P
= Stop Condition
SA
= Slave Acknowledge
MA
= Master Acknowledge
NA
= No Acknowledge
W
= Write
R
= Read
X
= Don’t Care
AD1 and AD0 are two-state address pins.
Table 5. Device Address Lookup
AD1 Address Pin
AD0 Address Pin
0
0
1
0
0
1
1
1
I
2
C Device Address
0011000
0011010
1001100
1001110
GENERIC INTERFACE
Table 6. Generic Interface Format
7-Bit Device Address
(See Table 5)
Slave Address Byte
S
R/W
SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Instruction Byte
Data Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2
C1
C0
Command Description
0
0
0
Operation Between Interface and RDAC.
0
0
1
Operation Between Interface and EEPROM.
0
1
0
Operation Between Interface and Write Protection Register. See Table 10.
1
0
0
NOP.
1
0
1
Restore EEPROM to RDAC.
1
1
0
Store RDAC to EEPROM.
WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address
(See Table 5)
Slave Address Byte
S
0
SA 0
0
0
0
0
0
0
0
SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Data Byte
Instruction Byte
Table 9. Writing to EEPROM Register
7-Bit Device Address
(See Table 5)
Slave Address Byte
S
0
SA 0
0
1
0
0
0
0
0
SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Data Byte
Instruction Byte
Table 10. Activating/Deactivating Software Write Protect
7-Bit Device Address
(See Table 5)
Slave Address Byte
S
0
SA 0
1
0
0
0
0
0
0
SA 0
0
0
0
0
0
0
WP SA P
Instruction Byte
Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the
command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
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