参数资料
| 型号： | AD5259BRMZ5-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 5K 256POS 10MSOP |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 5k |
| 电路数： | 1 |
| 温度系数： | 标准值 500 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 2.7 V ~ 3.3 V，4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 配用： | AD5259EVAL-ND - BOARD EVAL FOR AD5259 DGTL POT |
Data Sheet
AD5259
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time Between Stop
and Start
t1
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
μs
tSU;STA Setup Time for Repeated
Start Condition
t5
0.6
μs
tHD;DAT Data Hold Time
t6
0
0.9
μs
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and
SCL Signals
t8
300
ns
tR Rise Time of Both SDA and
SCL Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
0.6
μs
EEPROM Data Storing Time
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at
Power On2
tEEMEM_RESTORE1
VDD rise time dependent. Measure without
decoupling capacitors at VDD and GND.
300
μs
EEPROM Data Restoring Time upon
Restore Command2
tEEMEM_RESTORE2
VDD = 5 V.
300
μs
EEPROM Data Rewritable Time3
tEEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
100
700
kCycles
Data Retention5
100
Years
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
05026-004
t1
t2
t3
t8
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 4. I2C Interface Timing Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5259EVAL | 功能描述:BOARD EVAL FOR AD5259 DGTL POT RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD5259EVAL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| A-D525AKG-TAXB3 | 制造商:Assmann Electronics Inc 功能描述: |
| AD526 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision, Dual-Channel Instrumentation Amplifier |
| AD5260 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit Dual Nonvolatile Memory Digital Potentiometer |
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