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参数资料
| 型号： | AD5259EVAL2 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 数字电位计 |
| 英文描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 中文描述： | 非易失，I2C兼容256级，数字电位器 |
| 文件页数： | 5/24页 |
| 文件大小： | 1039K |
| 代理商： | AD5259EVAL2 |
AD5259
TIMING CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10% or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; 40°C < T
Table 2.
Parameter
I
2
C INTERFACE TIMING
CHARACTERISTICS
1
SCL Clock Frequency
t
BUF
Bus Free Time Between Stop
and Start
t
HD;STA
Hold Time (Repeated Start)
Rev. A | Page 5 of 24
A
< +85°C, unless otherwise noted.
Symbol
Conditions
Min
Typ
Max
Unit
f
SCL
t
1
0
1.3
400
kHz
μs
t
2
After this period, the first clock pulse is
generated.
0.6
μs
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated
Start Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and
SCL Signals
t
R
Rise Time of Both SDA and
SCL Signals
t
SU;STO
Setup Time for Stop Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at
Power On
2
EEPROM Data Restoring Time upon
Restore Command
2
EEPROM Data Rewritable Time
3
FLASH/EE MEMORY RELIABILITY
Endurance
4
Data Retention
5
t
3
t
4
t
5
1.3
0.6
0.6
μs
μs
μs
t
6
t
7
t
8
0
100
0.9
300
μs
ns
ns
t
9
300
ns
t
10
t
EEMEM_STORE
t
EEMEM_RESTORE1
V
DD
rise time dependent. Measure without
decoupling capacitors at V
DD
and GND.
V
DD
= 5 V.
0.6
26
300
μs
ms
μs
t
EEMEM_RESTORE2
300
μs
t
EEMEM_REWRITE
100
540
700
100
μs
kCycles
Years
1
Standard I
2
C mode operation guaranteed by design.
2
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3
Delay time after power-on PRESET prior to writing new EEPROM data.
4
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
5
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
0
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
P
S
S
SCL
SDA
P
Figure 4. I
2
C Interface Timing Diagram
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