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| 型号： | AD5260BRU200-REEL7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | 200K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
| 封装： | TSSOP-14 |
| 文件页数： | 3/20页 |
| 文件大小： | 859K |
| 代理商： | AD5260BRU200-REEL7 |
REV. 0
–3–
AD5260/AD5262
Parameter
INTERFACE TIMING CHARACTERISTICS apply to all parts
6, 12
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
13
CS
Setup Time
CS
High Pulsewidth
Reset Pulsewidth
CLK Fall to
CS
Rise Hold Time
CS
Rise to Clock Rise Setup
Symbol
Conditions
Min
Typ
Max
Unit
f
CLK
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock level high or low
20
10
10
1
5
20
50
0
10
R
L
= 1 k
, C
L
< 20pF
160
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil.
×
105 mil. 9,345 sq. mil.
1
Typicals represent average readings at 25
°
C and V
DD
= +5 V, V
SS
= –5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V, V
SS
= –5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0V. DNL
specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V, V
SS
= –5 V, V
L
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
12
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using V
L
= 5 V.
13
Propagation delay depends on value of V
DD
, R
L
, and C
L
.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
°
C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
A
X
– B
X
, A
X
– W
X
, B
X
– W
X
Intermittent
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40
°
C to +85
°
C
Maximum Junction Temperature (T
J MAX
) . . . . . . . . . . . 150
°
C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
°
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
Thermal Resistance
3
θ
JA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
°
C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°
C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3
Package Power Dissipation = (T
J MAX
– T
A
)/
θ
JA
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