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| 型号： | AD5260BRUZ20-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC DCP 1CH 20K SPI 14-TSSOP TR |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 20k |
| 电路数： | 1 |
| 温度系数： | 标准值 35 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 4 线 SPI（芯片选择） |
| 电源电压： | 4.5 V ~ 16.5 V，±4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
AD5260/AD5262
Rev. A | Page 15 of 24
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device and
operate up to 15 V maximum voltage. Changing the programmed
VR settings is accomplished by clocking an 8-/9-bit serial data
word into the SDI (serial data input) pin. For the AD5262, the
format of this data word is one address bit. A0 represents the
first bit, B8, followed by eight data bits, B7 to B0, with MSB
format. See Table 7 for the AD5262 address assignment to decode
the location of the VR latch receiving the serial register data in
Bit B7 through Bit B0. VR outputs can be changed one at a time
in random sequence. The AD5260/AD5262 preset to a midscale,
simplifying fault condition recovery at power-up. Midscale can
also be achieved at any time by asserting the PR pin. Both parts
have an internal power-on preset that places the wiper in a
midscale preset condition at power-on. Operation of the power-
on preset function depends only on the state of the VL pin.
The AD5260/AD5262 contain a power shutdown SHDN pin
that places the RDAC in an almost zero power consumption
state where Terminals Ax are open circuited and the Wiper W
is connected to B, resulting in only leakage currents being con-
sumed in the VR structure. In the shutdown mode, the VR latch
settings are maintained so that, when returning to operational
mode from power shutdown, the VR settings return to their
previous resistance values.
Table 7. AD5262 Address Decode Table
A0
Latch Loaded
0
RDAC1
1
RDAC2
DIGITAL INTERFACING
The AD5260/AD5262 contain a 4-wire SPI-compatible digital
interface (SDI, SDO, CS, and CLK). For the AD5260, the 8-bit
serial word must be loaded with the MSB first. The format of
the word is shown in
. For the AD5262, the 9-bit serial
word must be loaded with Address Bit A0 first, then the MSB
of the data. The format of the word is shown in
.
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
A1
W1
B1
VDD
CS
CLK
SDO
A2
W2
B2
GND
RDAC
LATCH
2
PR
RDAC
LATCH
1
PR
SDI
VL
VSS
SHDN
POWER-
ON
PRESET
EN
ADDR
DEC
02
695-
0
48
Figure 47. AD5262 Block Diagram
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register. Stand-
ard logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 47 shows more detail of the inter-
nal digital circuitry. When CS is low, the clock loads data into
the serial input register on each positive clock edge (see
).
Table 8. Truth Table1
CLK
CS
PR
SHDN
Register Activity
Low
High
No SR effect, enables SDO pin.
↑
Low
High
Shift one bit in from the SDI pin.
The eighth previously entered
bit is shifted out of the SDO pin.
X
↑
High
Load SR data into RDAC latch.
X
High
No operation.
X
Low
High
Sets all RDAC latches to half
scale, wiper centered, and SDO
latch cleared.
X
High
↑
High
Latches all RDAC latches to 0x80.
X
High
Low
Open circuits all Resistor A
terminals, connects W to B, and
turns off SDO output transistor.
1
↑ = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in Table 1 determine the
data valid time requirements. The AD5260 uses an 8-bit serial
input data register word that is transferred to the internal
RDAC register when the CS line returns to logic high. For the
AD5262, the last nine bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder, enabling one of two positive edge-triggered AD5262
RDAC latches (see
).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5260BRUZ50 | 功能描述:IC DGTL POT 50K SPI 14-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD5260BRUZ50-REEL7 | 功能描述:IC DGTL POT SNGL 50K 14-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5262 | 制造商:AD 制造商全称:Analog Devices 功能描述:256-Position and 33-Position Digital Potentiometers |
| AD5262BRU20 | 功能描述:IC POT DUAL 20K 256POS 16TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5262BRU200 | 功能描述:IC POT DUAL 200K 256POS 16TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
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