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参数资料
| 型号： | AD5271BCPZ-20-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC RHEOSTAT 5V 50-TP 256 10MSOP |
| 标准包装： | 1 |
| 接片： | 256 |
| 电阻（欧姆）： | 20k |
| 电路数： | 1 |
| 温度系数： | 标准值 5 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 4 线串行 |
| 电源电压： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 标准包装 |
| 其它名称： | AD5271BCPZ-20-RL7DKR |
AD5270/AD5271
Data Sheet
Rev. F | Page 22 of 24
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The nominal resistance between Terminal W and Terminal A, RWA,
is 20 kΩ, 50 kΩ, or 100 kΩ and has 1024-/256-tap points accessed
by the wiper terminal. The 10-/8-bit data in the RDAC latch is
decoded to select one of the 1024 or 256 possible wiper settings.
The AD5270 and AD5271 contain an internal ±1% resistor
tolerance calibration feature that can be disabled or enabled,
enabled by default, or by programming Bit C2 of the control
register (see Table 13 and Table 14).
The digitally programmed output resistance between the W
terminal and the A terminal, RWA, is calibrated to give a
maximum of ±1% absolute resistance error over both the full
supply and temperature ranges. As a result, the general
equations for determining the digitally programmed output
resistance between the W terminal and the A terminal are the
following:
For the AD5270
WA
R
D
R
1024
)
(
(1)
For the AD5271
WA
R
D
R
256
)
(
(2)
where:
D
is the decimal equivalent of the binary code loaded in the
10-/8-bit RDAC register.
RWA
is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper-
ating in, take care to limit the current between Terminal A to
Terminal W to the maximum continuous current of ±3 mA or
a pulse current specified in Table 8. Otherwise, degradation or
possible destruction of the internal switch contact can occur.
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP
pin, as shown in Figure 46, on power-up and throughout the
operation of the AD5270/AD5271.
AD5270/
AD5271
50_OTP
MEMORY
BLOCK
EXT_CAP
C1
1F
VSS
08
077
-00
8
Figure 46. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the
AD5270/AD5271 define the boundary conditions for proper
2-terminal digital resistor operation. Supply signals present on
Terminal A and Terminal W that exceed VDD or VSS are clamped
by the internal forward-biased diodes, see Figure 47.
VSS
VDD
A
W
08
077
-00
9
Figure 47. Maximum Terminal Voltages Set by VDD and VSS
The ground pins of the AD5270/AD5271 devices are primarily
used as digital ground references. To minimize the digital ground
bounce, join the AD5270/AD5271 ground terminal remotely
to the common ground. The digital input control signals to the
AD5270/AD5271 must be referenced to the device ground pin
(GND), and must satisfy the logic level defined in the
Specifications section. An internal level shift circuit ensures that
the common-mode voltage range of the three terminals extends
from VSS to VDD, regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Terminal W (see Figure 47), it is important to
power VDD/VSS first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD/VSS are powered unintentionally. The ideal power-up
sequence is VSS, GND, VDD, digital inputs, VA, and VW. The
order of powering VA, VW, and the digital inputs is not
important as long as they are powered after VDD/VSS.
As soon as VDD is powered, the power-on preset activates which
first sets the RDAC to midscale and then restores the last pro-
grammed 50-TP value to the RDAC register.
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