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参数资料
| 型号： | AD5273BRJ100-REEL7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 64-Position OTP Digital Potentiometer |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8 |
| 封装： | MO-178BA, SOT-23, 8 PIN |
| 文件页数： | 16/20页 |
| 文件大小： | 987K |
| 代理商： | AD5273BRJ100-REEL7 |
AD5273
–16–
FET N
1
. N
1
power handling must be adequate to dissipate
(V
IN
–V
OUT
) I
L
power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
reference such as ADR421, ADR03, or ADR370 can be applied
at the A terminal of the digital potentiometer.
Programmable Current Source
A programmable current source can be implemented with the
circuit shown in Figure 15. The load current is simply the voltage
across terminals B-to-W of the AD5273 divided by R
S
. Notice
at zero-scale, the A terminal of the AD5273 will be at –2.048 V,
which makes the wiper voltage clamped at ground potential.
Dependent on the load, Equation 5 is therefore valid only at cer-
tain codes. For example, when the compliance voltage V
L
equals
half of the V
REF
, the current can be programmed from midscale
to full-scale of the AD5273.
I
L
GND
V
IN
SLEEP
REF191
2
U1
+5V
4
6
3
0 TO (2.048 + V
L
)
V
OUT
C1
1 F
B
A
W
R
S
102
100
R
L
V
L
–2.048 + V
L
–5V
OP1177
V–
+5V
V+
U2
U3
AD5273
Figure 15. Programmable Current Source
I
V
(
D
R
D
L
REF
S
=
￥
￡
￡
)/6432
63
(5)
Gain Control Compensation
As seen in Figure 16, the digital potentiometers are commonly
used in gain controls or sensor transimpedance amplifier signal
conditioning applications.
U1
C2
4.7pF
R2A
B
W
100k
V
O
V
I
C1
R1
47k
Figure 16. Typical Noninverting Gain Amplifier
In both applications, one of the digital potentiometer terminals is
connected to the op amp inverting node with finite terminal capaci-
tance C1. It introduces a zero for the 1
o
term with 20 dB/dec
whereas a typical op amp GBP has –20 dB/dec characteristics. A
large R2 and finite C1 can cause this zero’s frequency to fall well
below the crossover frequency. Thus the rate of closure becomes
40 dB/dec and the system has 0° phase margin at the crossover
frequency. The output may ring or in the worst case oscillate when
the input is a step function. Similarly, it is also likely to ring when
switching between two gain values because this is equivalent to a
step change at the input. To reduce the effect of C1, users should
also configure B or A rather than W terminal at the inverting node.
Depending on the op amp GBP, reducing the feedback resistor may
extend the zero’s frequency far enough to overcome the problem.
A better approach is to include a compensation capacitor C2 to
cancel the effect caused by C1. Optimum compensation occurs
when R1 C1 = R2 C2. This is not an option because of the
variation of R2. As a result, one may use the relationship above
and scale C2 as if R2 is at its maximum value. Doing so may
overcompensate by slowing down the settling time when R2 is
set at low values. As a result, C2 should be found empirically for
a given application. In general, C2 in the range of a few pF to no
more than a few tenths of a pF is adequate for the compensation.
There is also a W terminal capacitance connected to the output
(not shown); its effect on stability is less significant so that the
compensation may not be necessary unless the op amp is driving
a large capacitive load.
Programmable Low-Pass Filter
In A/D conversion applications, it is common to include an anti-
aliasing filter to band-limit the sampling signal. To minimize various
system redesigns, users may use two 1 k AD5273s to construct a
generic second-order Sallen Key low-pass filter. Since the AD5273
is a single supply device, the input must be dc offset when an ac
signal is applied to avoid clipping at ground. This is illustrated in
Figure 17. The design equations are:
V
V
S
Q
1
S
O
I
O
O
O
=
+
+
w
w
w
2
2
2
(6)
w
O
R1R2C1C2
=
(7)
Q
R1C1
R2C2
=
+
1
1
(8)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where
Q
= 0.707, let
C
1 be
twice the size of
C
2 and let
R
1 =
R
2. As a result,
R
1 and
R
2 can
be adjusted to the same setting to achieve the desirable bandwidth.
V
O
AD8601
+2.5V
U1
–2.5V
V+
V–
C1
C
R1
R2
A
B
W
A
B
W C2
C
ADJUSTED TO
SAME SETTINGS
V
I
Figure 17. Sallen Key Low-Pass Filter
Level Shift for Different Voltages Operation
When users need to interface a 2.5 V controller with the AD5273,
a proper voltage level shift must be employed so that the digital
potentiometer can be read from or written to the controller;
Figure 18 shows one of the implementations. M1 and M2 should
be low threshold N-Ch Power MOSFETs such as FDV301N.
REV. 0
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| AD5273BRJ1-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD5273BRJ50-R2 | 功能描述:IC DGTL POT 50K 64POS SOT23-8 RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:2,500 系列:XDCP™ 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 ±300 ppm/°C 存储器类型:非易失 接口:I²C（设备位址） 电源电压:2.7 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:14-TSSOP 包装:带卷 (TR) |
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