参数资料
型号: AD5273BRJ50-REEL7
厂商: ANALOG DEVICES INC
元件分类: 数字电位计
英文描述: 64-Position OTP Digital Potentiometer
中文描述: 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8
封装: MO-178BA, SOT-23, 8 PIN
文件页数: 17/20页
文件大小: 987K
代理商: AD5273BRJ50-REEL7
AD5273
–17–
2.5V
CONTROLLER
2.7V–5.5V
AD5273
Rp
Rp
Rp
Rp
V
DD1
= 2.5V
V
DD2
= 5V
G
G
S
D
M1
S
D
M2
SDA1
SCL1
SDA2
SCL2
Figure 18. Level Shift for Different Voltage Operation
Resistance Scaling
The AD5273 offers 1 k , 10 k , 50 k , and 100 k nominal
resistances. For users who need to optimize the resolution with
an arbitrary full-range resistance, the following techniques can
be the solutions. Applicable only to the voltage divider mode, by
paralleling a discrete resistor as shown in Figure 19, a propor-
tionately lower voltage appears at terminal A–B. This translates
into a finer degree of precision because the step size at terminal
W will be smaller. The voltage can be found as:
V
D
( )
=
R
(
3
R
/ /
R
R
R
D
V
W
AB
+
AB
DD
)
/ /
2
2
256
(9)
R1
R2
B
A
V
DD
R3
W
Figure 19. Lowering the Nominal Resistance
Figure 19 shows that the digital potentiometer changes steps lin-
early. On the other hand, log taper adjustment is usually preferred in
applications like volume control. Figure 20 shows another way of
resistance scaling. In this circuit, the smaller the R2 with respect
to R
AB
, the more the pseudo log taper characteristic it behaves.
The wiper voltage is simply:
V
D
( )
=
R
D
( )
+
D
R
R
D
( )
R
R
V
W
WB
WA
WB
I
( )
/ /
/ /
2
2
(10)
V
I
R1
B
A
R2
V
O
W
Figure 20. Resistor Scaling with Log Adjustment
Characteristics
Resolution Enhancement
Borrowed from ADI’s patented RDAC segmentation technique,
users can configure three AD5273s to double the resolution. (See
Figure 21.) First, U3 must be paralleled with a discrete resistor
R
P
that is chosen to be equal to a step resistance (R
P
= R
AB
/64). We
may see that adjusting U1 and U2 together forms the coarse 6-bit
adjustment and adjusting U3 alone forms the finer 6-bit adjust-
ment. As a result, the effective resolution becomes 12-bit.
U1
A1
B1
W1
U2
A2
B2
W3
W2
U3
A3
B3
R
P
COARSE
ADJUSTMENT
FINE
ADJUSTMENT
Figure 21. Double the Resolution in Rheostat Mode Operation
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentiometers.
Configured as a potentiometer divider, the –3 dB bandwidth of
the AD5273 (1 k resistor) measures 6 MHz at
half scale. TPCs
15–18 provide the large signal BODE plot characteristics of the
four available resistor versions 1 k , 10 k , 50 k ,
and 100 k .
Figure 22 shows a parasitic simulation model. The code following
Figure 22 provides a macro model net list for the 1 k device:
55pF
C
A
25pF
C
25pF
A
B
1k
W
C
W
Figure 22. Circuit Simulation Model for RDAC = 1 k
Macro Model Net List for RDAC
.PARAM D = 63, RDAC = 1E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/63)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/63*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
REV. 0
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