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参数资料
| 型号： | AD5274BRMZ-20-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/28页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 20K 256POS 10MSOP |
| 标准包装： | 1,000 |
| 接片： | 256 |
| 电阻（欧姆）： | 20k |
| 电路数： | 1 |
| 温度系数： | 标准值 5 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C |
| 电源电压： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
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AD5272/AD5274
Data Sheet
Rev. D | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
VSS
2
A
3
W
4
10
9
8
SCL
ADDR
7
5
EXT_CAP
SDA
6
GND
AD5272/
AD5274
TOP VIEW
(Not to Scale)
RESET
08
07
6-
0
4
Figure 4. MSOP Pin Configuration
ADDR
VDD 1
VSS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6 GND
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
AD5272/
AD5274
(EXPOSED
PAD)
08
07
6
-04
0
Figure 5. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.
10
ADDR
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).
EPAD
Exposed Pad
(LFCSP Only)
Leave floating or tie to VSS.
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