参数资料
型号: AD5274BRMZ-20
厂商: Analog Devices Inc
文件页数: 17/28页
文件大小: 0K
描述: IC DGTL POT 20K 256POS 10MSOP
标准包装: 50
接片: 256
电阻(欧姆): 20k
电路数: 1
温度系数: 标准值 5 ppm/°C
存储器类型: 非易失
接口: I²C
电源电压: 2.7 V ~ 5.5 V,±2.5 V ~ 2.75 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
产品目录页面: 787 (CN2011-ZH PDF)
AD5272/AD5274
Data Sheet
Rev. D | Page 24 of 28
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP pin
(see Figure 47) on power-up and throughout the operation of
the AD5272/AD5274.
AD5272/
AD5274
50_OTP
MEMORY
BLOCK
EXT_CAP
C1
1F
VSS
08
076
-00
9
Figure 47. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the
AD5272/AD5274 define the boundary conditions for proper
2-terminal digital resistor operation. Supply signals present on
Terminal A and Terminal W that exceed VDD or VSS are clamped
by the internal forward-biased diodes (see Figure 48).
VSS
VDD
A
W
08
076
-10
9
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
The ground pins of the AD5272/AD5274 devices are primarily
used as digital ground references. To minimize the digital
ground bounce, join the AD5272/AD5274 ground terminal
remotely to the common ground. The digital input control
signals to the AD5272/AD5274 must be referenced to the
device ground pin (GND) and satisfy the logic level defined in
the Specifications section. An internal level shift circuit ensures
that the common-mode voltage range of the three terminals
extends from VSS to VDD, regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Terminal W (see Figure 48), it is important to
power VDD/VSS first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD/VSS are powered unintentionally. The ideal power-up
sequence is VSS, GND, VDD, digital inputs, VA, and VW. The
order of powering VA, VW, and digital inputs is not important
as long as they are powered after VDD/VSS.
As soon as VDD is powered, the power-on preset activates, which
first sets the RDAC to midscale and then restores the last
programmed 50-TP value to the RDAC register.
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