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| 型号： | AD5282BRU200 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 10-Bit, 40MSPS ADC Dual Ch., Low Power 48-TQFP -40 to 85 |
| 中文描述： | DUAL 200K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16 |
| 封装： | MO-153AB, TSSOP-16 |
| 文件页数： | 8/10页 |
| 文件大小： | 156K |
| 代理商： | AD5282BRU200 |
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
condition, Figure 2. In Read mode, the master will issue a
No Acknowledge for the 9
th
clock pulse (i.e., the SDA line
remains high). The master will then bring the SDA line low
before the 10
th
clock pulse which goes high to establish a
STOP condition, Figure 3.
8
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the Write cycle, each Data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its Slave Address and Instruction Bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the Write mode has to start with a new Slave Address,
Instruction, and Data Bytes again. Similarly, a repeated Read
function of the RDAC is also allowed.
MULTIPLE DEVICES ON ONE BUS
Figure 5 shows four AD5282 devices on the same serial bus.
Each has a different slave address sine the state of their AD0 and
AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull downs in a
fully I
2
C compatible interface.
SDA SCL
AD1
AD5282
AD0
MASTER
SDA
SCL
Rp
Rp
+5V
SDA SCL
AD1
AD5282
AD0
SDA SCL
AD1
AD5282
AD0
SDA SCL
AD1
AD5282
AD0
VDD
VDD
VDD
Figure 5. Multiple AD5282 Devices on One Bus
LEVEL SHIFT FOR BI-DIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new
component may be optimized at another. When two systems
operate the same signal at two different voltages, proper method
of level shifting is needed. For instance, one can use a 3.3V
E
2
PROM to interface with a 5V digital potentiometer. A level
shift scheme is needed in order to enable a bi-directional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E
PROM. Figure 6
shows one of the techniques. M1 and M2 can be N-Ch FETs
2N7002 or low threshold FDV301N if V
DD
falls below 2.5V.
3.3V
E2PROM
5V
AD5282
SDA1
SCL1
SDA2
SCL2
Rp
Rp
Rp
Rp
VDD1= 3.3V
VDD2= 5V
D
D
S
S
G
G
M1
M2
Figure 6. Level Shift for different potential operation.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in figure 7. Applies to
digital input pins SDA, SCL, and
SHDN
.
340
V
SS
LOGIC
Figure 7. ESD Protection of digital pins
A,B,W
VSS
Figure 8. ESD Protection of Resistor Terminals
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