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参数资料
| 型号： | AD5302 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| 中文描述： | 2.5 V至5.5 V，230微安双通道轨至轨电压输出数模转换器8-/10-/12-Bit |
| 文件页数： | 3/16页 |
| 文件大小： | 207K |
| 代理商： | AD5302 |
REV. 0
–3–
AD5302/AD5312/AD5322
AC CHARACTERISTICS
1
(V
DD
= +2.5 V to +5.5 V; R
L
= 2 k
V
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless
otherwise noted.)
B Version
3
Parameter
2
Min
Typ
Max
Units
Conditions/Comments
Output Voltage Settling Time
AD5302
AD5312
AD5322
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
V
REF
= V
DD
= +5 V
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
6
7
8
0.7
12
0.10
0.01
0.01
200
–70
8
9
10
μ
s
μ
s
μ
s
V/
μ
s
nV-s
nV-s
nV-s
nV-s
kHz
dB
1 LSB Change Around Major Carry (011 . . . 11 to 100 . . . 00)
V
REF
= 2 V
±
0.1 V p-p. Unbuffered Mode
V
REF
= 2.5 V
±
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology.
3
Temperature range: B Version: –40
°
C to +105
°
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Units
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
33
13
13
0
5
4.5
0
100
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
to SCLK Active Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time
LDAC
Pulsewidth
SCLK Falling Edge to
LDAC
Rising Edge
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
(V
DD
= +2.5 V to +5.5 V; all specifications T
MIN
to T
MAX
unless otherwise noted)
SCLK
SYNC
DIN*
t
2
t
3
t
5
t
6
t
7
t
4
DB15
t
1
DB0
t
9
t
10
LDAC
LDAC
*SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER
t
8
Figure 1. Serial Interface Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| AD5322 | 12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to 85 |
| AD5322BRM | 12-bit, 210MSPS ADC with DDR LVDS/CMOS outputs 48-VQFN -40 to 85 |
| AD5302BRM | +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| AD5312 | Dual Rail-To-Rail,Voltage Output 10-Bit DACs(满幅度电压输出双10位D/A转换器) |
| AD5313BRU | +2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5302_11 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.5 V to 5.5 V, 230 ??A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| AD53020 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four Channel ECL Delay Line |
| AD53020JP | 制造商:Analog Devices 功能描述: |
| AD53028 | 制造商:Analog Devices 功能描述: |
| AD53029 | 制造商:Analog Devices 功能描述: |
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