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参数资料
| 型号： | AD5305BRMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT 2WIRE I2C 10-MSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 设置时间： | 6µs |
| 位数： | 8 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 5mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，单极；4 电压，双极 |
| 采样率（每秒）： | 167k |
AD5305/AD5315/AD5325
Rev. G | Page 4 of 24
A Version1
B Version1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
LOGIC INPUTS (A0
Input Current
±1
μA
Input Low Voltage, VIL
0.8
V
VDD = 5 V ± 10%
0.6
V
VDD = 3 V ± 10%
0.5
V
VDD = 2.5 V
Input High Voltage, VIH
2.4
V
VDD = 5 V ± 10%
2.1
V
VDD = 3 V ± 10%
2.0
V
VDD = 2.5 V
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)5
Input High Voltage, VIH
0.7
VDD
VDD +
0.3
0.7
VDD
VDD +
0.3
V
SMBus compatible at VDD < 3.6 V
Input Low Voltage, VIL
0.3
0.3 VDD
0.3
0.3 VDD
V
SMBus compatible at VDD < 3.6 V
Input Leakage Current, IIN
±1
μA
Input Hysteresis, VHYST
0.05
VDD
0.05
VDD
V
Input Capacitance, CIN
8
pF
Glitch Rejection
50
ns
Input filtering suppresses noise spikes
of less than 50 ns
LOGIC OUTPUT (SDA)5
Output Low Voltage, VOL
0.4
V
ISINK = 3 mA
0.6
V
ISINK = 6 mA
Three-State Leakage Current
±1
μA
Three-State Output
Capacitance
8
pF
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
600
900
600
900
μA
VDD = 2.5 V to 3.6 V
500
700
500
700
μA
IDD (Power-Down Mode)
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
0.2
1
0.2
1
μA
IDD = 4 μA (maximum) during
0 readback on SDA
VDD = 2.5 V to 3.6 V
0.08
1
0.08
1
μA
IDD = 1.5 μA (maximum) during
0 readback on SDA
1 Temperature range (A, B version): 40°C to +105°C; typical at +25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5 Guaranteed by design and characterization, not production tested.
6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be
positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
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相关代理商/技术参数 |
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| AD5305BRMZ-REEL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.5 V to 5.5 V, 500 ??A, 2-Wire Interface Interface |
| AD5306 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| AD53062 | 制造商:Analog Devices 功能描述: |
| AD53063-02 | 制造商:Analog Devices 功能描述: |
| AD53063-03 | 制造商:Analog Devices 功能描述: |
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