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参数资料
| 型号： | AD5310 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail Voltage Output 10-Bit DAC(满幅度电压输出10位D/A转换器) |
| 中文描述： | 轨至轨电压输出10位DAC（满幅度电压输出10位的D / A转换器） |
| 文件页数： | 9/12页 |
| 文件大小： | 204K |
| 代理商： | AD5310 |
AD5310
–9–
REV. 0
SYNC
Interrupt
In a normal write sequence, the
SYNC
line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if
SYNC
is brought high before the
16th falling edge this acts as an interrupt to the write sequence.
T he shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 23.
Power-On-Reset
T he AD5310 contains a power-on-reset circuit which controls
the output voltage during power-up. T he DAC register is filled
with zeros and the output voltage is 0 V. It remains there until
a valid write sequence is made to the DAC. T his is useful in
applications where it is important to know the state of the out-
put of the DAC while it is in the process of powering up.
Power-Down Modes
T he AD5310 contains four separate modes of operation. T hese
modes are software-programmable by setting two bits (DB13
and DB12) in the control register. T able I shows how the state
of the bits corresponds to the mode of operation of the device.
T able I. Modes of Operation for the AD5310
DB13
0
DB12
0
Operating Mode
Normal Operation
Power-Down Modes
1 k
to GND
100 k
to GND
T hree-State
0
1
1
1
0
1
When both bits are set to 0, the part works normally with its
normal power consumption of 140
μ
A at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. T his has the
advantage that the output impedance of the part is known
while the part is in power-down mode. T here are three differ-
ent options. T he output is connected internally to GND through a
1 k
resistor, a 100 k
resistor or it is left open-circuited (T hree-
State). T he output stage is illustrated in Figure 24.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
Figure 24. Output Stage During Power-Down
T he bias generator, the output amplifier, the resistor string and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. T he time to
exit power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s for
V
DD
= 3 V. See Figure 18 for a plot.
MICROPROCE SSOR INT E RFACING
AD5310 to ADSP-2101/ADSP-2103 Interface
Figure 25 shows a serial interface between the AD5310 and the
ADSP-2101/ADSP-2103. T he ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT T ransmit Alternate Framing
Mode. T he ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured as
follows: Internal Clock Operation, Active Low Framing, 16-Bit
Word Length. T ransmission is initiated by writing a word to the
T x register after the SPORT has been enabled.
SCLK
ADSP-2101/
ADSP-2103*
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
SCLK
AD5310*
TFS
Figure 25. AD5310 to ADSP-2101/ADSP-2103 Interface
DB15
DB0
SCLK
SYNC
DIN
DB15
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
FALLING EDGE
INVALID WRITE SEQUENCE:
SYNC
HIGH BEFORE 16
TH
FALLING EDGE
Figure 23.
SYNC
Interrupt Facility
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