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| 型号： | AD5311 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 2-Wire Serial Input, Voltage Output 10-Bit DACs(二线串入,电压输出,10位D/A转换器) |
| 中文描述： | 2线串行输入，电压输出10位DAC（二线串入，电压输出，10位的D / A转换器） |
| 文件页数： | 3/8页 |
| 文件大小： | 320K |
| 代理商： | AD5311 |
3
AD5301/11/21 Prelim Technical Information
Prelim. H1 8/98
PRELMNARY
t10
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Units
Conditions/Comments
F
SCL
t
1
t
2
t
3
t
4
t
5
t
62
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
7
t
8
t
9
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time Between a STOP Condition and a
START Condition.
t
t
10
300
20 + 0.1C
b3
250
300
20 + 0.1C
b3
400
50
ns max
ns min
ns max
ns max
ns min
pF max
ns max
t
11
t
11
t
F
, Fall Time of SDA when transmitting.
t
F
, Fall Time of both SCL and SDA when receiving
C
b
t
SP4
Capacitive Load for Each Bus Line.
Pulse width of spike Suppressed.
NOTES
1
See Figure 1.
2
A master device must provide a hold time of at least 300ns for the SDA signal (referred to the V
IH min
of the SCL signal) in order to bridge the undefined region of
SCL's falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
and t
F
measured between 0.3V
DD
and 0.7V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50ns.
TIMING CHARACTERISTICS
1
(V
DD
= +2.5 V to +5.5 V . All specifications T
MIN
to T
MAX
unless otherwise noted)
Figure 1. 2-Wire Serial Interface Timing Diagram.
SDA
SCL
t9
t4
t3
t6
t2
t11
t5
t7
t4
t8
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
t1
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