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参数资料
| 型号： | AD5312BRM |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO10 |
| 封装： | MO-187BA, MSOP-10 |
| 文件页数： | 13/16页 |
| 文件大小： | 207K |
| 代理商： | AD5312BRM |
REV. 0
AD5302/AD5312/AD5322
–13–
AD5302/AD5312/AD5322 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5302/AD5312/
AD5322 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives
SCLK of the AD5302/AD5312/AD5322, while RXD drives the
serial data line of the part. The
SYNC
signal is again derived
from a bit programmable pin on the port. In this case port line
P3.3 is used. When data is to be transmitted to the AD5302/
AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 trans-
mits data only in 8-bit bytes; thus only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format that has the LSB first.
The AD5302/AD5312/AD5322 requires its data with the MSB
as the first bit received. The 80C51/80L51 transmit routine
should take this into account.
DIN
SCLK
SYNC
P3.3
TXD
RXD
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5302/
AD5312/
AD5322*
Figure 34. AD5302/AD5312/AD5322 to 80C51/80L51
Interface
AD5302/AD5312/AD5322 to MICROWIRE Interface
Figure 35 shows an interface between the AD5302/AD5312/
AD5322 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5302/AD5312/AD5322 on the rising edge
of the SK.
DIN
SCLK
SYNC
CS
SK
SO
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5302/
AD5312/
AD5322*
Figure 35. AD5302/AD5312/AD5322 to MICROWIRE
Interface
APPLICATIONS INFORMATION
Typical Application Circuit
The AD5302/AD5312/AD5322 can be used with a wide range
of reference voltages, especially if the reference inputs are con-
figured to be unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0 V to V
DD
. More typically, the AD5302/AD5312/AD5322 may
be used with a fixed, precision reference voltage. Figure 36
shows a typical setup for the AD5302/AD5312/AD5322 when
using an external reference. If the reference inputs are unbuf-
fered, the reference input range is from 0 V to V
DD
, but if the
on-chip reference buffers are used, the reference range is reduced.
Suitable references for 5 V operation are the AD780 and REF192
(2.5 V references). For 2.5 V operation, a suitable external
reference would be the REF191, a 2.048 V reference.
1
m
F
V
REF
A
V
REF
B
AD5302/AD5312/
AD5322
SCLK
DIN
SYNC
V
DD
GND
V
OUT
A
V
OUT
B
V
DD
= +2.5V TO +5.5V
V
OUT
EXT
REF
AD780/REF192
WITH V
= +5V
OR REF191 WITH
V
DD
= +2.5V
SERIAL
INTERFACE
Figure 36.AD5302/AD5312/AD5322 Using External
Reference
If an output range of 0 V to V
DD
is required when the reference
inputs are configured as unbuffered (for example 0 V to +5 V),
the simplest solution is to connect the reference inputs to V
DD
.
As this supply may not be very accurate and may be noisy, the
AD5302/AD5312/AD5322 may be powered from the reference
voltage; for example, using a 5 V reference such as the REF195,
as shown in Figure 37. The REF195 will output a steady supply
voltage for the AD5302/AD5312/AD5322 The current required
from the REF195 is 300
μ
A supply current and approximately
30
μ
A into each of the reference inputs. This is with no load on
the DAC outputs. When the DAC outputs are loaded, the
REF195 also needs to supply the current to the loads. The total
current required (with a 10 k
load on each output) is:
360
μ
A
+ 2(5
V
/10
k
) = 1.36
mA
The load regulation of the REF195 is typically 2 ppm/mA which
results in an error of 2.7 ppm (13.5
μ
V) for the 1.36 mA current
drawn from it. This corresponds to a 0.0007 LSB error at 8-bits
and 0.011 LSB error at 12 bits.
相关PDF资料 |
PDF描述 |
|---|---|
| AD5302 | +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| AD5322 | 12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to 85 |
| AD5322BRM | 12-bit, 210MSPS ADC with DDR LVDS/CMOS outputs 48-VQFN -40 to 85 |
| AD5302BRM | +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
| AD5312 | Dual Rail-To-Rail,Voltage Output 10-Bit DACs(满幅度电压输出双10位D/A转换器) |
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