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| 型号： | AD5316BRU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT QUAD W/BUFF 16TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 96 |
| 设置时间： | 7µs |
| 位数： | 10 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 4.5mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，单极；4 电压，双极 |
| 采样率（每秒）： | 143k |
AD5306/AD5316/AD5326
Rev. F | Page 4 of 24
A Version1
B Version1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
Short-Circuit Current
25
mA
VDD = 5 V.
16
mA
VDD = 3 V.
Power-Up Time
2.5
μs
Coming out of power-
down mode; VDD = 5 V.
5
μs
Coming out of power-
down mode; VDD = 3 V.
LOGIC INPUTS
(Excluding SCL, SDA)6
Input Current
±1
μA
VIL, Input Low Voltage
0.8
V
VDD = 5 V ± 10%.
0.6
V
VDD = 3 V ± 10%.
0.5
V
VDD = 2.5 V.
VIH, Input High Voltage
1.7
V
VDD = 2.5 V to 5.5 V;
TTL and 1.8 V CMOS
compatible.
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)6
VIH, Input High Voltage
0.7 VDD
VDD + 0.3
0.7 VDD
VDD + 0.3
V
SMBus compatible at
VDD < 3.6 V.
VIL, Input Low Voltage
0.3
+0.3 VDD
0.3
+0.3 VDD
V
SMBus compatible at
VDD < 3.6 V.
IIN, Input Leakage Current
±1
μA
VHYST, Input Hysteresis
0.05 VDD
V
See Figure 20.
CIN, Input Capacitance
8
pF
Glitch Rejection
50
ns
Input filtering suppresses
noise spikes of less than
50 ns.
LOGIC OUTPUT (SDA)6
VOL, Output Low Voltage
0.4
V
ISINK = 3 mA.
0.6
V
ISINK = 6 mA.
Three-State Leakage Current
±1
μA
Three-State Output
Capacitance
8
pF
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
VIH = VDD and VIL = GND;
interface inactive.
VDD = 4.5 V to 5.5 V
500
900
500
900
μA
All DACs in unbuffered
mode.
Buffered mode, extra
current is typically x mA
per DAC, where
x = 5 μA + VREF/RDAC.
VDD = 2.5 V to 3.6 V
400
750
400
750
μA
IDD (Power-Down Mode)
VIH = VDD and VIL = GND;
interface inactive.
VDD = 4.5 V to 5.5 V
0.3
1
0.3
1
μA
IDD = 3 μA (max) during
readback on SDA.
VDD = 2.5 V to 3.6 V
0.09
1
0.09
1
μA
IDD = 1.5 μA (max) during
readback on SDA.
1 Temperature range (A, B versions): 40°C to +105°C; typical at +25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization; not production tested.
7 For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, VREF = VDD,
the offset plus gain error must be positive.
8 Interface inactive; all DACs active. DAC outputs unloaded.
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