参数资料
型号: AD5323BRUZ-REEL7
厂商: Analog Devices Inc
文件页数: 1/28页
文件大小: 0K
描述: IC DAC 12BIT DUAL R-R 16-TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1,000
设置时间: 8µs
位数: 12
数据接口: 串行
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 2.5mW
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
输出数目和类型: 2 电压,单极;2 电压,双极
采样率(每秒): 125k
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323
Rev. B
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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Tel: 781.329.4700
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1999–2007 Analog Devices, Inc. All rights reserved.
FEATURES
AD5303: 2 buffered 8-bit DACs in 1 package
A version: ±1 LSB INL, B version: ±0.5 LSB INL
AD5313: 2 buffered 10-bit DACs in 1 package
A version: ±4 LSB INL, B version: ±2 LSB INL
AD5323: 2 buffered 12-bit DACs in 1 package
A version: ±16 LSB INL, B version: ±8 LSB INL
16-lead TSSOP package
Micropower operation: 300 μA @ 5 V (including reference
current)
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on-reset to 0 V
SDO daisy-chaining option
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered
voltage output DACs in a 16-lead TSSOP package that operate
from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-to-
rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on reset circuit, which ensures that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. There is also an asynchronous active low CLR pin that
clears both DACs to 0 V. The outputs of both DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the
current consumption of the devices to 200 nA at 5 V (50 nA
at 3 V) and provides software-selectable output loads while
in power-down mode. The parts may also be used in daisy-
chaining applications using the SDO pin.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is 1.5 mW at 5 V and 0.7 mW at
3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
DAC
REGISTER
POWER-DOWN
LOGIC
BUFFER
STRING
DAC
STRING
DAC
AD5303/AD5313/AD5323
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGIC
SCLK
POWER-ON
RESET
VDD
VREFA
VOUTA
VOUTB
GND
VREFB
LDAC
DIN
00
47
2-
0
01
SYNC
CLR
PD
BUF B
BUFFER
SDO
DCEN
BUF A
RESISTOR
NETWORK
RESISTOR
NETWORK
GAIN-SELECT
LOGIC
Figure 1.
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