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参数资料
| 型号： | AD5326ARU-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT QUAD W/BUFF 16TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 设置时间： | 8µs |
| 位数： | 12 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 4.5mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，单极；4 电压，双极 |
| 采样率（每秒）： | 125k |
AD5306/AD5316/AD5326
Rev. F | Page 19 of 24
However, if the master sends an ACK and continues clocking
SCL (no stop is sent), the DAC retransmits the same two bytes
of data on SDA. This allows continuous readback of data from
the selected DAC register.
Alternatively, the user can send a start followed by the address
with R/W = 1. In this case, the previously loaded pointer
settings are used and readback of data can start immediately.
DOUBLE-BUFFERED INTERFACE
The AD5306/AD5316/AD5326 DACs have double-buffered
interfaces consisting of two banks of registers: input registers
and DAC registers. The input registers are connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC registers contain the digital code used by the resistor
strings.
Access to the DAC registers is controlled by the LDAC pin.
When LDAC is high, the DAC registers are latched and the
input registers can change state without affecting the contents of
the DAC registers. When LDAC is low, however, the DAC
registers become transparent and the contents of the input
registers are transferred to them.
Double-buffering is useful if the user requires simultaneous
updating of all DAC outputs. The user may write to each of the
input registers individually and then, by pulsing the LDAC
input low, all outputs update simultaneously.
These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time that LDAC was low. Normally, when LDAC is low, the
DAC registers are filled with the contents of the input registers.
In the AD5306/AD5316/AD5326, the part updates the DAC
register only if the input register has been changed since the last
time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
LOAD DAC INPUT LDAC
LDAC transfers data from the input registers to the DAC
registers and, therefore, updates the outputs. The LDAC
function enables double-buffering of the DAC data, GAIN,
and BUF. There are two LDAC modes: synchronous mode and
asynchronous mode.
In synchronous mode, the DAC registers are updated after new
data is read in on the rising edge of the eighth SCL pulse. LDAC
can be tied permanently low or pulsed as in Figure 2.
In asynchronous mode, the outputs are not updated at the same
time the input registers are written to. When LDAC goes low,
the DAC registers are updated with the contents of the input
registers.
POWER-DOWN MODE
The AD5306/AD5316/AD5326 have very low power consump-
tion, dissipating typically at 1.2 mW with a 3 V supply and
2.5 mW with a 5 V supply. Power consumption can be reduced
further when the DACs are not in use by putting them into
power-down mode, which is selected by setting the PD pin low
or by setting Bit 12 (PD) of the data-word to 0.
When the PD pin is high and the PD bit is set to 1, all DACs work
normally with a typical power consumption of 500 μA at 5 V
(400 μA at 3 V). In power-down mode, however, the supply
current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are
powered down. Not only does the supply current drop, but each
output stage is internally switched from the output of its ampli-
fier, making it open-circuit. This has the advantage that the
outputs are three-state while the part is in power-down mode
and provides a defined input condition for whatever is connected
to the output of the DAC amplifiers. The output stage is shown
in Figure 35.
POWER-DOWN
CIRCUITRY
RESISTOR
STRING DAC
02066-035
AMPLIFIER
VOUT
Figure 35. Output Stage During Power-Down
The bias generator, output amplifiers, resistor strings, and all
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the registers
are unaffected when in power-down. In fact, it is possible to
load new data into the input registers and DAC registers during
power-down. The DAC outputs update as soon as the PD pin
goes high or the PD bit is reset to 1. The time to exit power-
down is typically 2.5 μs for VDD = 5 V and 5 μs for VDD = 3 V.
This is the time from the rising edge of the eighth SCL pulse or
from the rising edge of PD to when the output voltage deviates
from its power-down voltage (see Figure 23).
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相关代理商/技术参数 |
参数描述 |
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| AD5326ARUZ | 功能描述:IC DAC 12BIT QUAD W/BUFF 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5326ARUZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.5 V to 5.5 V, 400 ??A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs |
| AD5326BRU | 功能描述:IC DAC 12BIT QUAD W/BUFF 16TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5326BRU-REEL | 制造商:Analog Devices 功能描述:DAC 4-CH Resistor-String 12-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 4-CH RES-STRING 12-BIT 16TSSOP - Tape and Reel |
| AD5326BRU-REEL7 | 功能描述:IC DAC 12BIT QUAD W/BUFF 16TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
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