参数资料
型号: AD5336BRUZ
厂商: Analog Devices Inc
文件页数: 16/20页
文件大小: 0K
描述: IC DAC 10BIT QUAD VOUT 28-TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 50
设置时间: 7µs
位数: 10
数据接口: 并联
转换器数目: 4
电压电源: 单电源
功率耗散(最大): 4.5mW
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
输出数目和类型: 4 电压,单极;4 电压,双极
采样率(每秒): 143k
产品目录页面: 782 (CN2011-ZH PDF)
REV. 0
AD5334/AD5335/AD5336/AD5344
–5–
AD5334 FUNCTIONAL BLOCK DIAGRAM
VOUTA
BUFFER
GND
AD5334
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
BUFFER
POWER-ON
RESET
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
8-BIT
DAC
8-BIT
DAC
INPUT
REGISTER
VREFC/D
INTER-
FACE
LOGIC
VDD
VREFA/B
GAIN
DB7
DB0
CS
WR
A0
A1
CLR
LDAC
.
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
AD5334 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1VREFC/D
Unbuffered Reference Input for DACs C and D.
2VREFA/B
Unbuffered Reference Input for DACs A and B.
3VOUTA
Output of DAC A. Buffered Output with Rail-to-Rail Operation.
4VOUTB
Output of DAC B. Buffered Output with Rail-to-Rail Operation.
5VOUTC
Output of DAC C. Buffered Output with Rail-to-Rail Operation.
6VOUTD
Output of DAC D. Buffered Output with Rail-to-Rail Operation.
7
GND
Ground Reference Point for All Circuitry on the Part.
8
CS
Active Low Chip Select Input. This is used in conjunction with
WR to write data to the parallel interface.
9
WR
Active Low Write Input. This is used in conjunction with
CS to write data to the parallel interface.
10
A0
LSB Address Pin for Selecting which DAC Is to Be Written to.
11
A1
MSB Address Pin for Selecting which DAC Is to Be Written to.
12
LDAC
Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
13
PD
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14
VDD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10
F capacitor in parallel with a 0.1 F capacitor to GND.
15–22
DB0–DB7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
23
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF
24
CLR
Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5334 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5334
LDAC
A1
A0
WR
CS
VREFC/D
VREFA/B
VOUTA
VOUTB
GND
VOUTD
VOUTC
PD
VDD
DB0
DB1
DB2
CLR
GAIN
DB7
DB6
DB3
DB4
DB5
8-BIT
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