参数资料
型号: AD5341BRUZ-REEL
厂商: Analog Devices Inc
文件页数: 27/28页
文件大小: 0K
描述: IC DAC 12BIT SNGL VOUT 20-TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 2,500
设置时间: 8µs
位数: 12
数据接口: 并联
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 1.25mW
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): 125k
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 8 of 28
BUFFER
10-BIT
DAC
REGISTER
INPUT
REGISTER
INT
E
RF
ACE
L
O
G
IC
POWER-DOWN
LOGIC
DB8
DB7
DB0
..
CS
WR
CLR
LDAC
VREF
VDD
VOUT
PD
GND
AD5331
POWER-ON
RESET
10
9
7
6
13
20
1
DB9 2
GAIN 8
3
12
4
11
5
06
85
2-
005
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
VREF
VOUT
CLR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
PD
TOP VIEW
(Not to Scale)
AD5331
10-BIT
DB8
DB9
06
85
2-
00
6
Figure 5. AD5331 Functional Block Diagram
Figure 6. AD5331 Pin Configuration
Table 6. AD5331 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DB8
Parallel Data Input.
2
DB9
Most Significant Bit of Parallel Data Input.
3
VREF
Unbuffered Reference Input.
4
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
5
GND
Ground reference point for all circuitry on the part.
6
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9
CLR
Active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20
DB0 to DB7
Eight Parallel Data Inputs.
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