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参数资料
| 型号： | AD534K |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | ADC |
| 英文描述： | Dual 14-bit 105MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| 中文描述： | 内部设置的精密集成电路乘数 |
| 文件页数： | 5/12页 |
| 文件大小： | 159K |
| 代理商： | AD534K |
AD534
REV. B
–5–
FUNCTIONAL DESCRIPTION
Figure 2 is a functional block diagram of the AD534. Inputs are
converted to differential currents by three identical voltage-to-
current converters, each trimmed for zero offset. The product
of the X and Y currents is generated by a multiplier cell using
Gilbert’s translinear technique. An on-chip “Buried Zener”
provides a highly stable reference, which is laser trimmed to
provide an overall scale factor of 10V. The difference between
XY/SF and Z is then applied to the high gain output amplifier.
This permits various closed loop configurations and dramati-
cally reduces nonlinearities due to the input amplifiers, a domi-
nant source of distortion in earlier designs. The effectiveness of
the new scheme can be judged from the fact that under typical
conditions as a multiplier the nonlinearity on the Y input, with
X at full scale (
±
10 V), is
±
0.005% of FS; even at its worst
point, which occurs when X =
±
6.4 V, it is typically only
±
0.05% of FS Nonlinearity for signals applied to the X input,
on the other hand, is determined almost entirely by the multi-
plier element and is parabolic in form. This error is a major
factor in determining the overall accuracy of the unit and hence
is closely related to the device grade.
V-1
–
X
1
X
2
V-1
–
Y
1
Y
2
V-1
–
Z
1
Z
2
SF
AD534
+V
S
–V
S
A
OUT
TRANSFER FUNCTION
V
O
= A (X
1
– Z
2
)
1
– X
2
) (Y
1
– Y
2
)
HIGH GAIN
OUTPUT
AMPLIFIER
+
+
+
STABLE
REFERENCE
AND BIAS
TRANSLINEAR
MULTIPLIER
ELEMENT
0.75 ATTEN
Figure 2. Functional Block Diagram
The generalized transfer function for the AD534 is given by:
V
OUT
=
A
(
X
1
X
2
)(
Y
1
Y
2
)
SF
(
Z
1
Z
2
)
where
A
= open loop gain of output amplifier, typically
70 dB at dc
X
,
Y
,
Z
= input voltages (full scale =
±
SF, peak =
±
1.25 SF)
SF
= scale factor, pretrimmed to 10.00 V but adjustable
by the user down to 3 V.
In most cases the open loop gain can be regarded as infinite,
and SF will be 10 V. The operation performed by the AD534,
can then be described in terms of equation:
(
X
1
X
2
)(
Y
1
Y
2
)
=
10
V
(
Z
1
Z
2
)
The user may adjust SF for values between 10.00 V and 3 V by
connecting an external resistor in series with a potentiometer
between SF and –V
S
. The approximate value of the total resis-
tance for a given value of SF is given by the relationship:
R
SF
=
5.4
K
SF
10
SF
Due to device tolerances, allowance should be made to vary R
SF
;
by
±
25% using the potentiometer. Considerable reduction in
bias currents, noise and drift can be achieved by decreasing SF.
This has the overall effect of increasing signal gain without the
customary increase in noise. Note that the peak input signal is
always limited to 1.25 SF (i.e.,
±
5 V for SF = 4 V) so the overall
transfer function will show a maximum gain of 1.25. The per-
formance with small input signals, however, is improved by
using a lower SF since the dynamic range of the inputs is now
fully utilized. Bandwidth is unaffected by the use of this option.
Supply voltages of
±
15 V are generally assumed. However,
satisfactory operation is possible down to
±
8 V (see Figure 16).
Since all inputs maintain a constant peak input capability of
±
1.25 SF some feedback attenuation will be necessary to
achieve output voltage swings in excess of
±
12 V when using
higher supply voltages.
OPERATION AS A MULTIPLIER
Figure 3 shows the basic connection for multiplication. Note
that the circuit will meet all specifications without trimming.
X
1
X
2
Y
1
Y
2
Z
1
Z
2
AD534
= (X
2
1
– X
2
) (Y
1
– Y
2
)
OUTPUT ,
6
12V PK
X INPUT
6
10V FS
6
12V PK
Y INPUT
6
10V FS
6
12V PK
+15V
OUT
–V
S
+V
S
–15V
OPTIONAL SUMMING
INPUT, Z,
6
10V PK
SF
Figure 3. Basic Multiplier Connection
In some cases the user may wish to reduce ac feedthrough to a
minimum (as in a suppressed carrier modulator) by applying an
external trim voltage (
±
30 mV range required) to the X or Y
input (see Figure 1). Figure 19 shows the typical ac feedthrough
with this adjustment mode. Note that the Y input is a factor of
10 lower than the X input and should be used in applications
where null suppression is critical.
The high impedance Z
2
terminal of the AD534 may be used to
sum an additional signal into the output. In this mode the out-
put amplifier behaves as a voltage follower with a 1 MHz small
signal bandwidth and a 20 V/
μ
s slew rate. This terminal should
always be referenced to the ground point of the driven system,
particularly if this is remote. Likewise, the differential inputs
should be referenced to their respective ground potentials to
realize the full accuracy of the AD534.
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PDF描述 |
|---|---|
| AD534KD | Dual 14-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| AD534KH | Dual 14-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| AD534L | Dual 14-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| AD534LD | Dual 14-bit 125MSPS ADC with serialized LVDS output 48-VQFN -40 to 85 |
| AD534LH | Internally Trimmed Precision IC Multiplier |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD534KCHIP | 制造商:AD 制造商全称:Analog Devices 功能描述:Internally Trimmed Precision IC Multiplier |
| AD534KCHIPS | 制造商:AD 制造商全称:Analog Devices 功能描述:Internally Trimmed Precision IC Multiplier |
| AD534KD | 功能描述:IC PREC MULTIPLIER 14-CDIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD534KD/+ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Multiplier/Divider |
| AD534KDZ | 功能描述:IC PREC MULTIPLIER 14-CDIP RoHS:是 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
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