参数资料
型号: AD5380BSTZ-3
厂商: Analog Devices Inc
文件页数: 3/40页
文件大小: 0K
描述: IC DAC 14BIT 40CHAN 3V 100LQFP
产品培训模块: Data Converter Fundamentals
DAC Architectures
产品变化通告: Redesign Change 28/Oct/2011
设计资源: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5380 (CN0007)
Output Channel Monitoring Using AD5380 (CN0008)
标准包装: 1
设置时间: 6µs
位数: 14
数据接口: I²C,并联,串行
转换器数目: 40
电压电源: 单电源
功率耗散(最大): 125mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
输出数目和类型: 40 电压,单极
采样率(每秒): 125k
Data Sheet
AD5380
Rev. C | Page 11 of 40
PARALLEL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 7.
Parameter1,2,3
Limit at T
MIN, TMAX
Unit
Description
t
0
4.5
ns min
REG0, REG1, address to WR rising edge setup time
t
1
4.5
ns min
REG0, REG1, address to WR rising edge hold time
t
2
20
ns min
CS pulse width low
t
3
20
ns min
WR pulse width low
t
4
0
ns min
CS to WR falling edge setup time
t
5
0
ns min
WR to CS rising edge hold time
t
6
4.5
ns min
Data to WR rising edge setup time
t
7
4.5
ns min
Data to WR rising edge hold time
t
8
20
ns min
WR pulse width high
t
700
ns min
Minimum WR cycle time (single-channel write)
t
10
30
ns max
WR rising edge to BUSY falling edge
t
670
ns max
BUSY pulse width low (single-channel update)
t
12
30
ns min
WR rising edge to LDAC falling edge
t
13
20
ns min
LDAC pulse width low
t
14
100
ns max
BUSY rising edge to DAC output response time
t
15
20
ns min
LDAC rising edge to WR rising edge
t
16
0
ns min
BUSY rising edge to LDAC falling edge
t
17
100
ns min
LDAC falling edge to DAC output response time
t
18
8
s typ
DAC output settling time
t
19
20
ns min
CLR pulse width low
t
20
35
smax
CLR pulse activation time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with t
R = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
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