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参数资料
| 型号： | AD5381 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC |
| 中文描述： | 40通道，3伏/ 5 V，单电源，12位，电压输出DAC |
| 文件页数： | 25/36页 |
| 文件大小： | 1200K |
| 代理商： | AD5381 |
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AD5381
HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. Reset is a negative edge-
sensitive input. The default corresponds to m at full-scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT 0 to VOUT 39 to 0 V. This sequence takes 270 μs. The
falling edge of RESET initiates the reset process; BUSY goes low
for the duration, returning high when RESET is complete. While
BUSY is low, all interfaces are disabled and all LDAC pulses are
ignored. When BUSY returns high, the part resumes normal
operation and the status of the RESET pin is ignored until the
next falling edge is detected.
Rev. A | Page 25 of 36
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low clears the contents of the DAC
registers to the data contained in the user configurable CLR
register and sets VOUT 0 to VOUT 39 accordingly. This func-
tion can be used in system calibration to load zero-scale and
full-scale to all channels. The execution time for a CLR is 35 μs.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the
AD5381. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
of x2, the BUSY output goes low. While BUSY is low, the user
can continue writing new data to the x1, m, or c registers, but no
DAC output updates can take place. The DAC outputs are
updated by taking the LDAC input low. If LDAC goes low while
BUSY is active, the LDAC event is stored and the DAC outputs
update immediately after BUSY goes high. The user may hold
the LDAC input permanently low, in which case the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled and any events on LDAC are ignored. The AD5381
contains an extra feature whereby a DAC register is not updated
unless its x2 register has been written to since the last time
LDAC was brought low. Normally, when LDAC is brought low,
the DAC registers are filled with the contents of the x2 registers.
However, the AD5381 will only update the DAC register if the
x2 data has changed, thereby removing unnecessary digital
crosstalk.
FIFO OPERATION IN PARALLEL MODE
The AD5381 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO Enable (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DVDD, the internal FIFO is enabled, allowing the
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO_EN pin is
sampled on power-up, and after a CLR or RESET, to deter-mine
if the FIFO is enabled. In either serial or I
2
C interface modes,
FIFO_EN should be tied low. Up to 128 successive instructions
can be written to the FIFO at maximum speed in parallel mode.
When the FIFO is full, any further writes to the device are
ignored. Figure 29 shows a comparison between FIFO mode
and non-FIFO mode in terms of channel update time. Figure 29
also outlines digital loading time.
NUMBER OF WRITES
T
μ
s
1
4
7
10
13
16
19
22
25
28
31
34
37
0
10
5
15
25
20
40
WITHOUT FIFO
(CHANNEL UPDATE TIME)
WITH FIFO
(CHANNEL UPDATE TIME)
WITH FIFO
(DIGITAL LOADING TIME)
0
Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)
POWER-ON RESET
The AD5381 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The
BUSY pin goes low during the power-on reset sequencing,
preventing data writes to the device.
POWER-DOWN
The AD5381 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 μA max and digital power consumption to
20 μA max. In power-down mode, the output amplifier can be
configured as a high impedance output or can provide a 100 k
load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier will elapse before the outputs settle
to their correct values.
相关PDF资料 |
PDF描述 |
|---|---|
| AD5381BST-3 | 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC |
| AD5381BST-3-REEL | CONNECTOR ACCESSORY |
| AD5381BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5381BST-5-REEL | 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC |
| AD5382BST-3-REEL | CONNECTOR ACCESSORY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ad5381bst-3 | 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk 制造商:Analog Devices 功能描述: |
| AD5381BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 40-CH Resistor-String 12-bit 100-Pin LQFP T/R |
| AD5381BST-5 | 制造商:Analog Devices 功能描述:DAC 40-CH Resistor-String 12-bit 100-Pin LQFP |
| AD5381BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 40-CH Resistor-String 12-bit 100-Pin LQFP T/R |
| AD5381BSTZ-3 | 功能描述:IC DAC 12BIT 40CHAN 3V 100LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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