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| 型号： | AD5382BST-3-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100 |
| 封装： | 14 X 14 MM, MS-026BED, LQFP-100 |
| 文件页数： | 33/40页 |
| 文件大小： | 616K |
| 代理商： | AD5382BST-3-REEL |
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AD5382
APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5382 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5382 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only, a star ground
point established as close to the device as possible.
Rev. 0 | Page 33 of 40
For supplies with multiple pins (AV
DD
, DV
DD
), these pins should
be tied together. The AD5382 should have ample supply bypass-
ing of 10 μF in parallel with 0.1 μF on each supply, located as
close to the package as possible and ideally right up against the
device. The 10 μF capacitors are the tantalum bead type. The
0.1 μF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.
The power supply lines of the AD5382 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the D
IN
and SCLK lines will help reduce crosstalk
between them (this is not required on a multilayer board
because there will be a separate ground plane, but separating the
lines will help). It is essential to minimize noise on the V
IN
and
REFIN lines.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but is not always possible with
a double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the solder side.
TYPICAL CONFIGURATION CIRCUIT
Figure 39 shows a typical configuration for the AD5382-5 when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied
together to a common AGND. AGND and DGND are
connected together at the AD5382 device. On power-up, the
AD5382 defaults to external reference operation. All AV
DD
lines
are connected together and driven from the same 5 V source. It
is recommended to decouple close to the device with a 0.1 μF
ceramic and a 10 μF tantalum capacitor. In this application, the
reference for the AD5382-5 is provided externally from either
an ADR421 or ADR431 2.5 V reference. Suitable external
references for the AD5382-3 include the ADR280 1.2 V
reference. The reference should be decoupled at the
REFOUT/REFIN pin of the device with a 0.1 μF capacitor.
0
ADR431/
ADR421
AD5382-5
AVDD
DVDD
SIGNAL
GND
DAC
GND
DGND
VOUT31
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
μ
F
10
μ
F
0.1
μ
F
0.1
μ
F
AVDD
DVDD
Figure 39. Typical Configuration with External Reference
Figure 40 shows a typical configuration when using the internal
reference. On power-up, the AD5382 defaults to an external
reference; therefore, the internal reference needs to be
configured and turned on via a write to the AD5382 control
register. Control Register Bit CR12 allows the user choose the
reference value; Bit CR 10 is used to select the internal
reference. It is recommended to use the 2.5 V reference when
AV
DD
= 5 V, and the 1.25 V reference when AV
DD
= 3 V.
0
AD5382
AVDD
DVDD
SIGNAL
GND
DAC
GND
DGND
VOUT31
VOUT0
AGND
REFOUT/REFIN
REFGND
0.1
μ
F
10
μ
F
0.1
μ
F
0.1
μ
F
AVDD
DVDD
Figure 40. Typical Configuration with Internal Reference
Digital connections have been omitted for clarity. The AD5382
contains an internal power- on reset circuit with a 10 ms
brownout time. If the power supply ramp rate exceeds 10 ms,
the user should reset the AD5382 as part of the initialization
process to ensure the calibration data gets loaded correctly into
the device.
相关PDF资料 |
PDF描述 |
|---|---|
| AD5382 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5-REEL | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5383BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
| AD5382BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BSTZ-3 | 功能描述:IC DAC 14BIT 32CHAN 3V 100LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5382BSTZ-5 | 功能描述:IC DAC 14BIT 32CH 5V 100-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5383BST | 制造商:Analog Devices 功能描述:- Bulk |
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