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参数资料
| 型号： | AD5384BBC-3REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 40CH 3V 100-CSPBGA |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 标准包装： | 400 |
| 设置时间： | 8µs |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 40 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 80mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（10x10） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 40 电压，单极 |
| 采样率（每秒）： | 125k |
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Data Sheet
AD5384
HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of the internal
registers to their power-on reset state. RESET is a negative edge-
sensitive input. The default corresponds to m at full scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT0 to VOUT39 to 0 V. The hardware reset activation time
takes 270 s. The falling edge of RESET initiates the reset
process; BUSY goes low during this process, returning high
when RESET is complete. While BUSY is low, all interfaces are
disabled, and all LDAC pulses are ignored. When BUSY returns
high, the device resumes normal operation, and the status of the
RESET pin is ignored until the next falling edge is detected. Do
not bring RESET low when the AD5384 is in power-down
mode.
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low loads the contents of the DAC
registers with the data contained in the user-configurable CLR
register, and sets VOUT0 to VOUT39 accordingly. Use this
function in system calibration to load zero scale and full scale to
all channels. The execution time for CLR is 35 s.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the
AD5384. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
of x2, the BUSY output goes low. While BUSY is low, the user
can continue writing new data to the x1, m, or c registers, but
no DAC output updates can take place. The DAC outputs are
updated by bringing the LDAC input low. If LDAC goes low
while BUSY is active, the LDAC event is stored, and the DAC
outputs update immediately after BUSY goes high. The user can
hold the LDAC input permanently low, in which case, the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled, and any events on LDAC are ignored. The AD5384
contains an extra feature, whereby a DAC register does not
update unless its x2 register has been written to since the last
time LDAC was brought low. Normally, when LDAC is brought
low, the DAC registers fill with the contents of the x2 registers.
However, the AD5384 updates the DAC register only if the x2
data has changed, thereby removing unnecessary digital
crosstalk.
POWER-ON RESET
The AD5384 contains a power-on reset generator and state
machine. The power-on reset generator resets all registers to a
predefined state and configures the analog outputs as high
impedance. The BUSY pin goes low during the power-on reset
sequencing, preventing data writes to the device.
POWER-DOWN FEATURE
The AD5384 contains a global power-down feature that puts all
channels into low power mode and reduces the analog power
consumption to 2 A maximum and digital power consumption
to 20 A maximum. In power-down mode, the output amplifier
can be configured as a high impedance output, or it can provide
a 100 k load to ground. The contents of all internal registers
remain in power-down mode. When exiting power-down
mode, the settling time of the amplifier elapses before the
outputs settle to their correct values.
POWER SUPPLY SEQUENCING
The power-on reset circuitry requires that the AVDDx is applied
before or within 10 ms of DVDDx, which ensures that the
registers are correctly loaded with their default values. If it is not
possible for AVDDx to be applied within 10 ms of DVDDx, a
software or hardware reset is used to load the default register
values.
Rev. B | Page 23 of 32
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相关代理商/技术参数 |
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| AD5384BBC-5 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD5384BBC-5REEL7 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD5384BBCZ-3 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD5384BBCZ-5 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD5384BBCZ-5REEL7 | 功能描述:14 Bit Digital to Analog Converter 40 100-CSBGA (10x10) 制造商:analog devices inc. 系列:denseDAC 包装:带卷（TR） 零件状态:有效 位数:14 数模转换器数:40 建立时间:8μs 输出类型:Voltage - Buffered 差分输出:无 数据接口:I2C，SPI，DSP 参考类型:外部， 内部 电压 - 电源，模拟:5V 电压 - 电源，数字:2.7 V ~ 5.5 V INL/DNL（LSB）:±4（最大），-1/+2（最大） 架构:电阻串 DAC 工作温度:-40°C ~ 85°C 封装/外壳:100-LFBGA，CSPBGA 供应商器件封装:100-CSBGA（10x10） 标准包装:400 |
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