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参数资料
| 型号： | AD5398BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/17页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT CURRENT-SINK 8LFCSP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 设置时间： | 250µs |
| 位数： | 10 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 8-LFCSP-VD（3x3） |
| 包装： | 标准包装 |
| 输出数目和类型： | 1 电流，单极 |
| 采样率（每秒）： | 31k |
| 产品目录页面： | 782 (CN2011-ZH PDF) |
| 其它名称： | AD5398BCPZ-REEL7DKR |
AD5398
Rev. B | Page 4 of 16
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Output Current Settling Time
250
μs
VDD = 5 V, RL = 25 Ω, LL = 680 μH
scale to scale change (0x100 to 0x300)
Slew Rate
0.3
mA/μs
Major Code Change Glitch Impulse
0.15
nA-s
1 LSB change around major carry
Digital Feedthrough3
0.06
nA-s
1 Temperature range is as follows: B Version: –40°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section.
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Parameter1
Limit at TMIN, TMAX
Unit
Description
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
t62
0.9
μs max
tHD, DAT, data hold time
0
μs min
t7
0.6
μs min
tSU, STA, setup time for repeated start
t8
0.6
μs min
tSU, STO, stop condition setup time
t9
1.3
μs min
tBUF, bus free time between a stop condition and a start condition
t10
300
ns max
tR, rise time of both SCL and SDA when receiving
0
ns min
May be CMOS driven
t11
250
ns max
tF, fall time of SDA when receiving
300
ns max
tF, fall time of both SCL and SDA when transmitting
20 + 0.1 Cb3
ns min
Cb
400
pF max
Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
05034-
002
SDA
t9
SCL
t3
t10
t11
t4
t6
t2
t5
t7
t1
t8
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
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