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参数资料
| 型号： | AD5429YRU-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 8BIT MULT 16-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 2,500 |
| 设置时间： | 30ns |
| 位数： | 8 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 3.5µW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 2.47M |
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Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 23 of 28
80C51/80L51-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 52. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line, SDIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;
therefore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and then a second write cycle is initiated
to transmit the second byte of data. Data on RxD is clocked out
of the microcontroller on the rising edge of TxD and is valid on
the falling edge of TxD. As a result, no glue logic is required
between the DAC and microcontroller interface. P1.1 is taken
high following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
requirement into account.
SCLK
TxD
80C51
*
SYNC
P1.1
SDIN
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
029
AD5429/AD5439/
AD5449*
Figure 52. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface
MC68HC11-to-AD5429/AD5439/AD5449 Interface
Figure 53 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The SPI on the MC68HC11
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured
by writing to the SPI control register (SPCR); see the MC68HC11
user manual. The SCK of the MC68HC11 drives the SCLK of
the DAC interface; the MOSI output drives the serial data line
(SDIN) of the AD5429/AD5439/AD5449.
SCLK
SCK
AD5429/AD5439/
AD5449*
SYNC
PC7
SDIN
MOSI
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
030
Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the SYNC
line is taken low (PC7). Data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the DAC, leave PC7 low after the first eight bits
are transferred and perform a second serial write operation to
the DAC. PC7 is taken high at the end of this procedure.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
MC68HC11, and, with SYNC low, the shift register clocks data
out on the rising edges of SCLK.
MICROWIRE-to-AD5429/AD5439/AD5449 Interface
Figure 54 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
SCLK
SK
MICROWIRE*
SYNC
CS
SDIN
SO
AD5429/AD5439/
AD5449*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
031
Figure 54. MICROWIRE-to-AD5429/AD5439/AD5449 Interface
PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual for
more information. In this example, the I/O port, RA1, is used to
provide a SYNC signal and enable the serial port of the DAC. This
microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 55 shows the connection diagram.
SCLK
SCK/RC3
PIC16C6x/7x*
SYNC
RA1
SDIN
SDI/RC4
AD5429/AD5439/
AD5449*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
032
Figure 55. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
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| AD5429YRU-REEL7 | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 8-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH R-2R 8BIT 16TSSOP - Tape and Reel |
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| AD5429YRUZ-REEL | 功能描述:IC DAC DUAL 8BIT MULT 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 设计资源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 标准包装:10,000 系列:- 设置时间:- 位数:12 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:SOT-23-8 薄型，TSOT-23-8 供应商设备封装:TSOT-23-8 包装:带卷 (TR) 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:2.7M |
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