
Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 15 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dual-
channel, current output DACs consisting of a standard inverting
for a single channel of the AD5449. The feedback resistor, RFBA,
has a value of R. The value of R is typically 10 kΩ (with a
minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1A and
IOUT2A are kept at the same potential, a constant current flows
into each ladder leg, regardless of digital input code. Therefore,
the input resistance presented at VREFA is always constant.
2R
S1
2R
S2
2R
S3
2R
S12
2R
DAC DATA LATCHES
AND DRIVERS
R
RFBA
IOUT1A
IOUT2A
VREFA
04464-006
RR
R
Figure 37. Simplified Ladder
Access is provided to the VREFx, RFBx, IOUT1x, and IOUT2x termi-
nals of the DACs, making the devices extremely versatile and
allowing them to be configured in several operating modes, such
as unipolar mode, bipolar output mode, or single-supply mode.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
D
V
2
/
where:
D
is the fractional representation of the digital word loaded to
the DAC.
D
= 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n
is the number of bits.
With a fixed 10 V reference, the circuit shown in
Figure 38 gives
a unipolar 0 V to 10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5429 DAC.
Table 5. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
VREF (255/256)
1000 0000
VREF (128/256) = VREF/2
0000 0001
VREF (1/256)
0000 0000
VREF (0/256) = 0
AD5429/
AD5439/
AD5449
04
46
4-
0
07
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
3. DAC B OMITTED FOR CLARITY.
IOUT1A
IOUT2A
VREFx
VDD
C1
A1
VOUT = 0V TO –VREF
AGND
R2
VDD
VREF
SDIN
GND
SCLK
SYNC
RFBA
R1
IF A1 IS A HIGH SPEED AMPLIFIER.
MICROCONTROLLER
Figure 38. Unipolar Operation