参数资料
| 型号： | AD5449YRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT MULT 16-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 96 |
| 设置时间： | 80ns |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 3.5µW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 2.47M |
| 产品目录页面： | 782 (CN2011-ZH PDF) |
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Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 21 of 28
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchron-
ization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling edge to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisy-
chain mode, the internal gating on SCLK is disabled. SCLK is
continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default; use
the control word to change the active edge) and is valid for the
next device on the falling edge of SCLK (default). By connecting
this line to the SDIN input on the next device in the chain,
a multidevice interface is constructed. For each device in the
system, 16 clock pulses are required. Therefore, the total number
of clock cycles must equal 16n, where n is the total number of
devices in the chain. See Figure 4.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used, after which SYNC can be
taken high. After the rising edge of SYNC, data is automatically
transferred from the input shift register of each device to the
addressed DAC.
When control bits = 0000, the device is in no operation mode.
This may be useful in daisy-chain applications in which the user
does not want to change the settings of a particular DAC in the
chain. Write 0000 to the control bits for that DAC; subsequent
data bits are ignored.
Standalone Mode
After power-on, write 1001 to the control word to disable daisy-
chain mode. The first falling edge of SYNC resets the serial
clock counter to ensure that the correct number of bits are
shifted in and out of the serial shift registers. A SYNC edge
during the 16-bit write cycle causes the device to abort the
current write cycle.
After the falling edge of the 16th SCLK pulse, data is automat-
ically transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous and synchronous
updates to the DAC output. The DAC is asynchronously updated
when this signal goes low. Alternatively, if this line is held perma-
nently low, an automatic or synchronous update mode is selected,
whereby the DAC is updated on the 16th clock falling edge when
the device is in standalone mode, or on the rising edge of SYNC
when the device is in daisy-chain mode.
Software LDAC Function
Load-and-update mode can also serve as a software update func-
tion, irrespective of the voltage level on the LDAC pin.
Table 11. DAC Control Bits
C3
C2
C1
C0
DAC
Function Implemented
0
A and B
No operation (power-on default)
0
1
A
Load and update
0
1
0
A
Initiate readback
0
1
A
Load input register
0
1
0
B
Load and update
0
1
0
1
B
Initiate readback
0
1
0
B
Load input register
0
1
A and B
Update DAC outputs
1
0
A and B
Load input registers
1
0
1
N/A
Disable daisy-chain
1
0
1
0
N/A
Clock data to shift register on rising edge
1
0
1
N/A
Clear DAC output to zero scale
1
0
N/A
Clear DAC output to midscale
1
0
1
N/A
Control word
1
0
N/A
Reserved
1
N/A
No operation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5449YRUZ-REEL | 功能描述:IC DAC DUAL 12BIT MULT 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5449YRUZ-REEL7 | 功能描述:IC DAC DUAL 12BIT MULT 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD544JH | 制造商:Rochester Electronics LLC 功能描述:ULTRA-LOW DRIFT OP AMP IC - Bulk |
| AD544JH/+ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD544KH | 制造商:AD 功能描述:544 ANALOG |
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