参数资料
型号: AD5452YRMZ-REEL7
厂商: Analog Devices Inc
文件页数: 24/28页
文件大小: 0K
描述: IC DAC 12BIT MULTIPLYING 8MSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
设计资源: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052)
Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053)
AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054)
Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
标准包装: 1,000
位数: 12
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
输出数目和类型: 1 电流,单极;1 电流,双极
采样率(每秒): 2.7M
Data Sheet
AD5450/AD5451/AD5452/AD5453
Rev. G | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: 40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VDD = 2.5 V to 5.5 V
Unit
Description
fSCLK
50
MHz max
Maximum clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
8
ns min
SYNC falling edge to SCLK active edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK active edge
t8
30
ns min
Minimum SYNC high time
Update Rate
2.7
MSPS
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
04587-002
SCLK
SYNC
DIN
DB15
DB0
t7
t3
t2
t6
t5
t4
t8
t1
Figure 2. Timing Diagram
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