参数资料
型号: AD5453YUJZ-REEL
厂商: Analog Devices Inc
文件页数: 7/28页
文件大小: 0K
描述: IC DAC 14BIT MULT TSOT23-8
产品培训模块: Data Converter Fundamentals
DAC Architectures
设计资源: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052)
Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053)
AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054)
Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
标准包装: 10,000
位数: 14
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-8 薄型,TSOT-23-8
供应商设备封装: TSOT-23-8
包装: 带卷 (TR)
输出数目和类型: 1 电流,单极;1 电流,双极
采样率(每秒): 2.7M
Data Sheet
AD5450/AD5451/AD5452/AD5453
Rev. G | Page 15 of 28
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is mea-
sured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum over the operating temperature
range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF 1 LSB. Gain error of the DACs is adjustable to zero with
external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when it is
turned off. For the IOUT1 terminal, it can be measured by loading
all 0s to the DAC and measuring the IOUT1 current.
Output Capacitance
Capacitance from IOUT1 to AGND.
Output Current Settling Time
The amount of time it takes for the output to settle to a specified
level for a full-scale input change. For these devices, it is specified
with a 100 resistor to ground. The settling time specification
includes the digital delay from the SYNC rising edge to the full-
scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s, depending
on whether the glitch is measured as a current or voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
1
5
4
3
2
V
THD
2
log
20
+
=
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa fb and 2fb fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
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