参数资料
型号: AD5543CRMZ-REEL7
厂商: Analog Devices Inc
文件页数: 8/20页
文件大小: 0K
描述: IC DAC 16BIT SRL 8MSOP
设计资源: Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151)
标准包装: 1,000
设置时间: 500ns
位数: 16
数据接口: 串行
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 55µW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
输出数目和类型: 1 电流,单极;1 电流,双极
AD5543/AD5553
Data Sheet
Rev. F | Page 16 of 20
02917-
127
VIN: USE THIS PIN TO POWER THE SDP
REQUIRES 4-7V 200mA
VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA
BOARD ID EEPROM (24LC64) MUST BE ON I2C BUS 0, ADDRESS IS AT USER DISCRETION
I2C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED
BMODE1: PULL UP WITH A 10k RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD
(CONNECTED TO BLACKFIN GPIO - USE I2C_0 FIRST)
MAIN I2C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED)
CONNECTOR
STANDARD
SDP
PARALLEL
PORT
SPORT
SPI
I2C
GENERAL
INPUT/OUTPUT
TIMERS
*
*NC ON BLACKFIN SDP
120
NC
119
NC
118
GND
117
GND
116
VIO(+3.3V)
115
GND
114
PAR_D22
113
PAR_D20
112
PAR_D18
111
PAR_D16
110
PAR_D15
109
GND
108
PAR_D12
107
PAR_D10
106
PAR_D8
105
PAR_D6
104
GND
103
PAR_D4
102
PAR_D2
101
PAR_D0
100
PAR_WR
99
PAR_INT
98
GND
97
PAR_A2
96
PAR_A0
95
PAR_FS2
94
PAR_CLK
93
GND
92
SPORT_RSCLK
91
SPORT_DR0
90
SPORT_RFS
89
SPORT_TFS
88
SPORT_DT0
87
SPORT_TSCLK
86
GND
85
SPI_SEL_A
84
SPI_MOSI
83
SPI_MISO
82
SPI_CLK
81
GND
80
SDA_0
79
SCL_0
78
GPIO1
77
GPIO3
76
GPIO5
75
GND
74
GPIO7
73
TMR_B
72
TMR_D
71
NC
70
NC
69
GND
68
NC
67
NC
66
NC
65
NC
64
NC
63
GND
62
UART_TX
61
BMODE1
60
RESET_IN
59
UART_RX
58
GND
57
NC
56
NC
55
NC
54
NC
53
NC
52
GND
51
NC
50
NC
49
TMR_C
48
TMR_A
47
GPIO6
46
GND
45
GPIO4
44
GPIO2
43
GPIO0
42
SCL_1
41
SDA_1
40
GND
39
SPI_SEL1/SPI_SS
38
SPI_SEL_C
37
SPI_SEL_B
36
GND
35
SPORT_INT
34
SPORT_DT3
33
SPORT_DT2
32
SPORT_DT1
31
SPORT_DR1
30
SPORT_DR2
29
SPORT_DR3
28
GND
27
PAR_FS1
26
PAR_FS3
25
PAR_A1
24
PAR_A3
23
GND
22
PAR_CS
21
PAR_RD
20
PAR_D1
19
PAR_D3
18
PAR_D5
17
GND
16
PAR_D7
15
PAR_D9
14
PAR_D11
13
PAR_D13
12
PAR_D14
11
GND
10
PAR_D17
9
PAR_D19
8
PAR_D21
7
PAR_D23
6
GND
5
USB_VBUS
4
GND
3
GND
2
NC
1
VIN
J2
1
A0
2
A1
3
A2
4
VSS
8
VCC
7
WP
6
SCL
5
SDA
U4
24LC64
USB_VBUS
3.3V_BF
SCLK
SDIN
/CS
START
3.3V_BF
STATUS
Figure 28. Schematic of SDP Interface
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