参数资料
型号: AD5546BRU
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC DAC 16BIT PARALL IN 28-TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
设计资源: Precision, Unipolar, Inverting Conversion Using AD5546/56 DAC (CN0022)
Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024)
Precision, Unipolar, Noninverting Configuration for the AD5546/56 DAC (CN0023)
Precision, AC Reference Signal Attenuator Using AD5546/56 Multiplying DAC (CN0025)
标准包装: 1
设置时间: 500ns
位数: 16
数据接口: 并联
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 55µW
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
输出数目和类型: 1 电流,单极;1 电流,双极
采样率(每秒): 2M
Data Sheet
AD5546/AD5556
Rev. D | Page 15 of 20
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 11 lists some of the references
available from Analog Devices that are suitable for use with this
range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources, they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit is
determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
VREF node (the voltage output node in this application) of the
DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 12 and Table 13.
Table 11. Suitable Analog Devices Precision References
Part No.
Output Voltage (V)
Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C)
ISS (mA)
Output Noise (V p-p)
Package(s)
10
0.05
3
1
20
SOIC-8
10
0.05
9
1
20
TSOT-5, SC70-5
5.0
0.06
3
1
10
SOIC-8
5.0
0.06
9
1
10
TSOT-5, SC70-5
2.5
0.1
3
1
6
SOIC-8
2.5
0.1
9
1
6
TSOT-5, SC70-5
3.0
0.1
3
1
10
SOIC-8
3.0
0.1
9
1
10
TSOT-5, SC70-5
2.048
0.05
3
0.5
1.75
SOIC-8, MSOP-8
2.50
0.04
3
0.5
1.75
SOIC-8, MSOP-8
3.00
0.04
3
0.5
2
SOIC-8, MSOP-8
5.00
0.04
3
0.5
3.4
SOIC-8, MSOP-8
2.500
0.04
3
0.8
3.5
SOIC-8, MSOP-8
5.000
0.04
3
0.8
8
SOIC-8, MSOP-8
2.5
0.16
9
0.12
5
TSOT-5
5.0
0.10
9
0.12
8
TSOT-5
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