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参数资料
| 型号： | AD5583YRVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT QUAD VOUT 48-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 2,500 |
| 设置时间： | 5µs |
| 位数： | 10 |
| 数据接口： | 并联 |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 功率耗散（最大）： | 30mW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，单极；4 电压，双极 |
| 采样率（每秒）： | 200k |
REV. A
AD5582/AD5583
–3–
ELECTRICAL CHARACTERISTICS
(VDD = 15 V, VSS = 0 V, DVDD = 5 V
10%, VREFH = 10 V, VREFL = 0 V,
–40 C < TA < +125 C, unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ
1
Max
Unit
STATIC PERFORMANCE
Resolution
2
N
AD5582
12
Bits
AD5583
10
Bits
Relative Accuracy
3
INL
–1
+1
LSB
Differential Nonlinearity
3
DNL
Monotonic
–1
LSB
Zero-Scale Error
VZSE
Data = 000H for AD5582
–2
+2
LSB
and AD5583
Gain Error
VGE
Data = 0xFFFH for AD5582
–2
+2
LSB
VGE
Data = 0x3FFH for AD5583
–4
+4
LSB
Full-Scale Tempco
4
TCVFS
1.5
ppm/
∞C
REFERENCE INPUT
VREFH Input Range
VREFH
VREFL + 0.5
VDD
V
VREFL Input Range
5
VREFL
VSS
VREFH – 0.5 V
Input Resistance
RREF
Data = 555H (Minimum RREF)12
20
k
W1
for AD5582 and 155H for AD5583
Input Capacitance
4
CREF
80
pF
REF Input Current
IREF
Data = 555H for AD5582
1000
mA
REF Multiplying Bandwidth
BWREF
Code = Full Scale
1.3
MHz
R1–R2 Matching
R1/R2
AD5582
±0.025
%
AD5583
±0.100
%
ANALOG OUTPUT
Output Current
6
IOUT
Data = 800H for AD5582 and
2
mA
200H for AD5583, VOUT
2 mV
Output Current
6
IOUT
Data = 800H for AD5582 and
200H for AD5583, VOUT
|–8 mV|
+20
mA
VOUT
15 mV
–20
mA
Capacitive Load
4, 7
CL
No Oscillation
Note 7
pF
Parameter
Symbol
Condition
Min
Typ
1
Max
Unit
SUPPLY CHARACTERISTICS
Single-Supply Voltage Range
VDD
VSS = 0 V
3
18
V
Dual-Supply Voltage Range
VDD/VSS
VDD = +2.7 V to +6.5 V,
–9
+9
V
VSS = –6.5 V to –2.7 V
Digital Logic Supply
DVDD
2.7
8
V
Positive Supply Current
6
IDD
VIL = 0 V, No Load
1.7
3
mA
Negative Supply Current
ISS
VIL = 0 V, No Load
1.5
3
mA
Power Dissipation
PDISS
VIL = 0 V, No Load
16
30
mW
Power Supply Sensitivity
PSS
VDD =
±5%
30
ppm/V
NOTES
1Typical specifications represent average readings measured at 25
∞C.
2DAC Output Equation: V
OUT = VREFL + [(VREFH – VREFL)
D/2
N], where D = data loaded in corresponding DAC Register A, B, C, D, and N equals the number of bits;
AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V REFH – VREFL)/4096 V and (VREFH – VREFL)/1024 V for AD5582 and AD5583, respectively.
3The first two codes (000
H, 001H) of the AD5583 and the first four codes (000 H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.
4These parameters are guaranteed by design and not subject to production testing.
5Dual-supply operation, V
REFL = VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.
6Short circuit output and supply currents are 24 mA and 25 mA, respectively.
7Part is stable under any capacitive loading conditions.
8The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.
Specifications subject to change without notice.
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