参数资料
型号: AD5735ACPZ-REEL7
厂商: Analog Devices Inc
文件页数: 4/48页
文件大小: 0K
描述: IC DAC QUAD VOLT CUR 64LFCSP
标准包装: 750
设置时间: 18µs
位数: 12
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 4
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
输出数目和类型: 4 电流,4 电压
采样率(每秒): *
AD5735
Data Sheet
Rev. C | Page 12 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PO
C
R
E
SET
AV
DD
CO
M
P
LV
_
A
–V
SENSE
_
A
+V
SENSE
_
A
CO
M
P
DC
_
A
V
B
OOS
T
_
A
V
OU
T
_
A
I OU
T
_
A
AV
SS
CO
M
P
LV
_
B
–V
SENSE
_
B
+V
SENSE
_
B
V
OU
T
_
B
CO
M
P
DC
_
B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R
SE
T
_
C
R
SE
T
_
D
REF
O
U
T
REF
IN
CO
M
P
LV
_
D
–V
S
E
NSE_
D
+V
SE
N
S
E_
D
CO
M
P
DC
_
D
V
B
OOS
T
_
D
V
OU
T
_
D
I OU
T
_
D
AV
SS
CO
M
P
LV
_
C
–V
S
E
NSE_
C
+V
SE
N
S
E_
C
V
OU
T
_
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RSET_B
RSET_A
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
CLEAR
ALERT
FAULT
COMPDCDC_C
IOUT_C
VBOOST_C
AVCC
SWC
GNDSWC
GNDSWD
SWD
AVSS
SWA
GNDSWA
GNDSWB
SWB
AGND
VBOOST_B
IOUT_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5735
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE
AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
0
9
961
-006
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RSET_B
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_B temperature drift performance. For more information, see the External Current Setting Resistor section.
2
RSET_A
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_A temperature drift performance. For more information, see the External Current Setting Resistor section.
3
REFGND
Ground Reference Point for Internal Reference.
4
REFGND
Ground Reference Point for Internal Reference.
5
AD0
Address Decode for the Device Under Test (DUT) on the Board.
6
AD1
Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using
7
SYNC
Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked
into the input shift register on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface
operates at clock speeds of up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
SDO
Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5).
11
DVDD
Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V.
12
DGND
Digital Ground.
13
LDAC
Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.
When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of
SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output
is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be
updated simultaneously. The LDAC pin must not be left unconnected.
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