参数资料
型号: AD573JNZ
厂商: Analog Devices Inc
文件页数: 9/10页
文件大小: 0K
描述: IC ADC 10BIT SAR REGISTER 20-DIP
标准包装: 18
位数: 10
采样率(每秒): 50k
数据接口: 并联
转换器数目: 1
功率耗散(最大): 800mW
电压电源: 双 ±
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 20-DIP(0.300",7.62mm)
供应商设备封装: 20-PDIP
包装: 管件
输入数目和类型: 1 个单端,单极;1 个单端,双极
产品目录页面: 777 (CN2011-ZH PDF)
AD573
–8–
It is also possible to write a faster-executing assembly-language
routine to control the AD573. Such a routine will require a de-
lay between starting and reading the converter. This can be eas-
ily implemented by calling the Apple’s WAIT subroutine (which
resides at location $FCA8) after loading the accumulator with a
number greater than or equal to two.
8085-Series Microprocessor Interface
The AD573 can also be used with 8085-series microprocessors.
These processors use separate control signals for RD and WR,
as opposed to the single R/W control signal used in the 6800/
6500 series processors.
There are two constraints related to operation of the AD573
with 8085-series processors. The first problem is the width of
the CONVERT pulse. The circuit shown in Figure 17 (essen-
tially the same as that shown in Figure 13) will produce a wide
enough CONVERT pulse when the 8085 is running at 5 MHz.
For 8085 systems running at slower clock rates (3 MHz), the
flip-flop-based circuit can be eliminated since the WR pulse will
be approximately 500 ns wide.
The other consideration is the access time of the AD573’s three-
state output data buffers, which is 250 ns maximum. It may be
necessary to insert wait states during RD operations from the
AD573. This will not be a problem in systems using memories
with comparable access times, since wait states will have already
been provided in the basic system design.
Figure 17. AD573–8085A Interface Connections
The following assembly-language subroutine can be used to
control an AD573 residing at memory locations 3000H and
3001H. The 10 bits of data are returned (left-justified) in the
DE register pair.
ADC:
LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS
MOV M, A
; START CONVERSION
MVI B, 06
; LOAD DELAY PERIOD
LOOP: DCR B
; DELAY LOOP
JNZ LOOP
;
MOV A, M
; READ LOW BYTE
ANI C0
; MASK LOWER 6 BITS
MOV E, A
; STORE CLEAN LOW BYTE IN E
INR L
; LOAD HIGH BYTE ADDRESS
MOV D, M
; MOVE HIGH BYTE TO D
RET
; EXIT
REV. B
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