参数资料
| 型号： | AD5790BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC VOLT OUT 20BIT 24LFCSP |
| 标准包装： | 1 |
| 设置时间： | 2.5µs |
| 位数： | 20 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ EP（4x5） |
| 包装： | 托盘 |
| 输出数目和类型： | 1 电压，双极 |
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AD5790
Data Sheet
Rev. D | Page 18 of 28
THEORY OF OPERATION
The AD5790 is a high accuracy, fast settling, single, 20-bit,
serial input, voltage-output DAC. It operates from a VDD supply
voltage of 7 V to 16.5 V and a VSS supply of 16.5 V to -2.5 V.
Data is written to the AD5790 in a 24-bit word format via a 3-wire
serial interface. The AD5790 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5790 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 20-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one of
63 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 14 bits of the data-word drive
Switches S0 to S13 of a 14-bit voltage mode R-2R ladder
network.
2R
S0
2R
S1
2R
S13
2R
E62
2R
E61
2R
E0
14-BIT R-2R LADDER
.....................
..........
.........
RR
R
VREFP
VREFN
VOUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
10
239-
05
0
Figure 49. DAC Ladder Structure
SERIAL INTERFACE
The AD5790 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/W bit, three address bits and
20 data bits as shown in Table 6. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19 to DB0
R/W
Register address
Register data
Table 7. Decoding the Input Shift Register
R/W
Register Address
Description
0
No operation (NOP). Used in readback operations.
0
1
Write to the DAC register.
0
1
0
Write to the control register.
0
1
Write to the clearcode register.
0
1
0
Write to the software control register.
1
0
1
Read from the DAC register.
1
0
1
0
Read from the control register.
1
0
1
Read from the clearcode register.
1 X is don’t care.
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