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参数资料
| 型号： | AD652AQ/+ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 779K |
| 描述： | IC V-F CONV SYNCH MONO 5V 16CDIP |
| 标准包装： | 25 |
| 类型： | 电压至频率 |
| 频率 - 最大： | 2MHz |
| 全量程： | ±50ppm/°C |
| 线性： | ±0.02% |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-CERDIP |
| 包装： | 管件 |
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AD652
Rev. C | Page 8 of 28
Another way to view this is that the output is a frequency of
approximately one-quarter of the clock that has been phase
modulated. A constant frequency can be thought of as
accumulating phase linearly with time at a rate equal to 2纅
radians per second. Therefore, the average output frequency,
which is slightly in excess of a quarter of the clock, requires
phase accumulation at a certain rate. However, since the SVFC
is running at exactly one-quarter of the clock, it does not
accumulate enough phase (see Figure 7). When the difference
between the required phase (average frequency) and the actual
phase equals 2? a step-in phase is taken where the deficit is
made up instantaneously. The output frequency is then a steady
carrier that has been phase modulated by a sawtooth signal (see
Figure 7). The period of the sawtooth phase modulation is the
time required to accumulate a 2? difference in phase between
the required average frequency and one quarter of the clock
frequency. The sawtooth phase modulation amplitude is 2?
TIME
TIME
?SPAN class="pst AD652SQ_2632819_4">MOD (t)
ACTUAL PHASE
EXPECTED
PHASE
PHASE
2?/SPAN>
2?/SPAN>
2?/SPAN>
PHASE
MODULATION
AVERAGE
CARRIER FREQUENCY
V
OUT
(t) = COS (2?/SPAN>?/SPAN>f
AVE
?SPAN class="pst AD652SQ_2632819_4">t +?SPAN class="pst AD652SQ_2632819_4">MOD (t))
Figure 7. Phase Modulation
The result of this synchronism is that the rate at which data may
be extracted from the series bit stream produced by the SVFC is
limited. The output pulses are typically counted during a fixed
gate interval and the result is interpreted as an average
frequency. The resolution of such a measurement is determined
by the clock frequency and the gate time. For example, if the
clock frequency is 4 MHz and the gate time is 4.096 ms, a
maximum count of 8,192 is produced by a full-scale frequency
of 2 MHz. Thus, the resolution is 13 bits.
OVERRANGE
Since each reset pulse is only one clock period in length, the
full-scale output frequency is equal to one-half the clock
frequency. At full scale, the current steering switch spends half
of the time on the summing junction; thus, an input current of
0.5 mA can be balanced. In the case of an overrange, the output
of the integrator op amp drifts in the negative direction and the
output of the comparator remains high. The logic circuits
simply settle into a divide-by-two of the clock state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD652AQ | 制造商:Analog Devices 功能描述:SEMICONDUCTORS LINEAR 制造商:Analog Devices 功能描述:V/F CONVERTER 2MHZ 0.02% 5V 16DIP 制造商:Analog Devices 功能描述:V/F CONVERTER, 2MHZ, 0.02%, 5V, 16DIP |
| AD652AQ/+ | 功能描述:IC V-F CONV SYNCH MONO 5V 16CDIP RoHS:否 类别:集成电路 (IC) >> PMIC - V/F 和 F/V 转换器 系列:- 标准包装:1 系列:- 类型:频率至电压 频率 - 最大:10kHz 全量程:- 线性:±0.3% 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:Digi-Reel® 其它名称:LM2917MX-8/NOPBDKR |
| AD652AQ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Monolithic Synchronous Voltage-to-Frequency Converter |
| AD652AQZ | 制造商:Analog Devices 功能描述:VFC Sync 2MHz 16-Pin CDIP 制造商:Analog Devices 功能描述:IC V/F-F/V CONVERTER DIP16 652 |
| AD652BQ | 功能描述:IC V-F CONVERTER SYNC 16-CDIP RoHS:否 类别:集成电路 (IC) >> PMIC - V/F 和 F/V 转换器 系列:- 标准包装:1 系列:- 类型:频率至电压 频率 - 最大:10kHz 全量程:- 线性:±0.3% 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:Digi-Reel® 其它名称:LM2917MX-8/NOPBDKR |
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