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| 型号： | AD654JNZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/12页 |
| 文件大小： | 354K |
| 描述： | IC V-F CONVERTER MONO 8-DIP |
| 标准包装： | 50 |
| 类型： | 电压至频率 |
| 频率 - 最大： | 500kHz |
| 全量程： | ±50ppm/°C |
| 线性： | ±0.2% |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 786 (CN2011-ZH PDF) |
AD654
6
REV.
and insure the supply, source and load are appropriate. If provision
is made to trim offset, begin by setting the input to 1/10,000 of
full scale. Adjust the offset pot until the output is 1/10,000 of
full scale (for example, 25 Hz for a FS of 250 kHz). This is most
easily accomplished using a frequency meter connected to the
output. The FS input should then be applied and the gain pot
should be adjusted until the desired FS frequency is indicated.
INPUT PROTECTION
The AD654 was designed to be used with a minimum of additional
hardware. However, the successful application of a precision IC
involves a good understanding of possible pitfalls and the use of
suitable precautions. Thus +V
IN
and R
T
pins should not be driven
more than 300 mV below V
S
. Likewise, Logic Common should
not drop more than 500 mV below V
S
. This would cause inter-
nal junctions to conduct, possibly damaging the IC. In addition
to the diode shown in Figures 1 and 2 protecting Logic Common,
a second Schottky diode (MBD101) can protect the AD654s
inputs from below V
S
inputs as shown in Figure 5. It is also
desirable not to drive +V
IN
and R
T
above +V
S
. In operation, the
converter will exhibit a zero output for inputs above (+V
S
3.5 V).
Also, control currents above 2 mA will increase nonlinearity.
The AD654s 80 dB dynamic range guarantees operation from a
control current of 1 mA (nominal FS) down to 100 nA (equiva-
lent to 1 mV to 10 V FS). Below 100 nA improper operation of
the oscillator may result, causing a false indication of input
amplitude. In many cases this might be due to short-lived noise
spikes which become added to input. For example, when scaled
to accept an FS input of 1 V, the 80 dB level is only 100 礦, so
when the mean input is only 60 dB below FS (1 mV), noise spikes
of 0.9 mV are sufficient to cause momentary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter or a guard ring around the R
T
pin. The
filter can be assembled using the bias current compensation
resistor discussed in the previous section. For an FS of 10 kHz,
a single-pole filter with a time constant of 100 ms will be suitable,
but the optimum configuration will depend on the application
and the type of signal processing. Noise spikes are only likely to
be a cause of error when the input current remains near its mini-
mum value for long periods of time; above 100 nA full integration
of additive input noise occurs. Like the inputs, the capacitor
terminals are sensitive to interference from other signals. The
timing capacitor should be located as close as possible to the
AD654 to minimize signal pickup in the leads. In some cases,
guard rings or shielding may be required.
AD654
MBD101
I
IN
Figure 5. Input Protection
DECOUPLING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 to
100 &) in the supply lines to provide a measure of decoupling
between the various circuits in the system. Ceramic capacitors
of 0.1 礔 to 1.0 礔 should be applied between the supply-
voltage pins and analog signal ground for proper bypassing on
the AD654. A proper ground scheme appears in Figure 6.
8
1
7
2
6
3
5
4
AD654
+5V
GND
DIGITAL
P.S.
10
0.1F
C
T
R
T
R
PU
f
OUT
GND
V
IN
Figure 6. Proper Ground Scheme
OUTPUT INTERFACING CONSIDERATION
The output stages design allows easy interfacing to all digital logic
families. The output NPN transistors emitter and collector are
both uncommitted. The emitter can be tied to any voltage between
V
S
and 4 volts below +V
S
, and the open collector can be pulled
up to a voltage 36 volts above the emitter regardless of +V
S
. The
high power output stage can sink over 10 mA at a maximum
saturation voltage of 0.4 V. The stage limits the output current
at 25 mA and can handle this limit indefinitely without damag-
ing the device.
NONLINEARITY SPECIFICATION
The preferred method of specifying nonlinearity error is in terms
of maximum deviation from the ideal relationship after calibrat-
ing the converter at full scale. This error will vary with the full
scale frequency and the mode of operation. The AD654 operates
best at a 150 kHz full-scale frequency with a negative voltage input;
the linearity is typically within 0.05%. Operating at higher fre-
quencies or with positive inputs will degrade the linearity as
indicated in the Specifications Table. Typical linearity at various
temperatures is shown in Figure 7.
FULL-SCALE FREQUENCY kHz
10
0.01
10
1
150
250
350
500
5
0.5
0.10
0.05
f
AMB
= 40C
f
AMB
= 0C TO +85C
Figure 7. Typical Nonlinearities at Different Full-Scale
Frequencies
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