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| 型号： | AD660ARZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT MONO W/VREF 24-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | DACPORT® |
| 设置时间： | 6µs |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字，双 ± |
| 功率耗散（最大）： | 625mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | 167k |
AD660
Rev. B | Page 17 of 20
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 μA current through a 0.5 Ω trace develops a voltage drop of
153 μV, which is 1 LSB at the 16-bit level for a 10 V full-scale
span. In addition to ground drops, inductive and capacitive
coupling need to be considered, especially when high accuracy
analog signals share the same board with digital signals. Finally,
power supplies need to be decoupled to filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide
PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes should also be used, with a
single interconnection point to minimize ground loops. Analog
signals should be routed as far as possible from digital signals
and should cross them at right angles.
One feature that the AD660 incorporates to help the user layout
is that the analog pins (+VCC, VEE, REF OUT, REF IN, SPAN/
BIPOLAR OFFSET, VOUT and AGND) are adjacent to help
isolate analog signals from digital signals.
SUPPLY DECOUPLING
The AD660 power supplies should be well filtered, well regulated,
and free from high frequency noise. Switching power supplies
are not recommended due to their tendency to generate spikes,
which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout
proximity between all power supply pins and ground. A 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor
provides adequate decoupling. VCC and VEE should be bypassed
to analog ground, while VLL should be decoupled to digital ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD660, associated analog circuitry, and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD660 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction is
not recommended; careful printed circuit construction is
preferred.
GROUNDING
The AD660 has two ground pins, designated analog ground
(AGND) and digital ground (DGND.) The analog ground pin is
the high quality ground reference point for the device. Any
external loads on the output of the AD660 should be returned
to analog ground. If an external reference is used, this should
also be returned to the analog ground.
If a single AD660 is used with separate analog and digital ground
planes, connect the analog ground plane to AGND and the digital
ground plane to DGND keeping lead lengths as short as possible.
Then connect AGND and DGND together at the AD660. If
multiple AD660 devices are used or the AD660 shares analog
supplies with other components, connect the analog and digital
returns together once at the power supplies rather than at each
chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD660ARZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Monolithic 16-Bit Serial/Byte DACPORT |
| AD660BN | 功能描述:IC DAC 16BIT MONO W/VREF 24-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD660BNZ | 功能描述:IC DAC 16BIT MONO W/VREF 24DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD660BNZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Monolithic 16-Bit Serial/Byte DACPORT |
| AD660BR | 功能描述:IC DAC 16BIT MONO W/VREF 24-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
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