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参数资料
| 型号： | AD7151BRMZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC CAP CONV 1CH ULT LP 10MSOP |
| 标准包装： | 3,000 |
| 类型： | 电容数字转换器 |
| 输入类型： | 电压 |
| 输出类型： | 数字 |
| 接口： | 2 线串口 |
| 电流 - 电源： | 120µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
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AD7151
Rev. 0 | Page 4 of 28
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
POWER REQUIREMENTS
VDD-to-GND Voltage
2.7
3.6
V
VDD = 3.3 V, nominal
70
80
μA
1
5
μA
Temperature ≤ 25°C
3
10
μA
Temperature = 85°C
1 Capacitance units: one picofarad (1 pF) = 1 × 1012 farad (F); one femtofarad (1 fF) = 1015 farad (F).
2 The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion
input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC
nominal input range.
3 Specification is not production tested but is supported by characterization data at initial product release.
4 Digital inputs equal to VDD or GND.
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CONVERTER
Conversion Time
10
ms
0.3
ms
2
ms
2
ms
See Figure 2.
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
μs
SCL Low Pulse Width, tLOW
1.3
μs
SCL, SDA Rise Time, tR
0.3
μs
SCL, SDA Fall Time, tF
0.3
μs
Hold Time (Start Condition), tHD;STA
0.6
μs
After this period, the first clock is generated.
Setup Time (Start Condition), tSU;STA
0.6
μs
Relevant for repeated start condition.
Data Setup Time, tSU;DAT
0.1
μs
Setup Time (Stop Condition), tSU;STO
0.6
μs
Data Hold Time (Master), tHD;DAT
10
ns
Bus-Free Time (Between Stop and Start Condition), tBUF
1.3
μs
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface
command.
4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface
command.
5 Sample tested during initial release to ensure compliance.
6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
tLOW
tR
tF
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tHD;STA
tSU;STO
tHIGH
SCL
PS
SDA
tBUF
07
08
6-
00
2
Figure 2. Serial Interface Timing Diagram
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| AD7152 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit Capacitance-to-Digital Converter |
| AD7152BRMZ | 功能描述:IC CDC 12BIT 2/4CH 10MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Data Converter Basics 标准包装:1 系列:- 类型:电机控制 分辨率（位）:12 b 采样率（每秒）:1M 数据接口:串行，并联 电压电源:单电源 电源电压:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:100-TQFP 供应商设备封装:100-TQFP（14x14） 包装:剪切带 (CT) 其它名称:296-18373-1 |
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