参数资料
型号: AD7233BNZ
厂商: Analog Devices Inc
文件页数: 8/8页
文件大小: 0K
描述: IC DAC 12BIT SRL W/AMP 8PDIP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1
系列: DACPORT®
设置时间: 10µs
位数: 12
数据接口: 串行
转换器数目: 1
电压电源: 双 ±
功率耗散(最大): 168mW
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
输出数目和类型: 1 电压,双极
采样率(每秒): 300k
AD7233
REV. B
–8–
C00989a-0-4/01(B)
PRINTED
IN
U.S.A.
AD7233-68HC11 Interface
Figure 8 shows a serial interface between the AD7233 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7233 while the MOSI output drives the serial data line.
The
SYNC signal is derived from a port line (PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. To load data to the AD7233, PC7 is kept
low after the first eight bits are transferred and a second byte of
data is then transferred serially to the AD7233. When the sec-
ond serial transfer is complete, the PC7 line is taken high. Fig-
ure 8 shows the
LDAC input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output of the DAC
will be updated on the sixteenth falling edge of SCK after the
respective
SYNC signal has gone low. Alternatively, the scheme
used in previous interfaces, whereby the
LDAC input is driven
from a timer, can be used.
LDAC
68HC11*
SYNC
SCLK
PC7
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7233*
MOSI
SDIN
Figure 8. AD7233 to 68HC11 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
14
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
AD7233–Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
B Version column added to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
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