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参数资料
| 型号： | AD7242KR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs |
| 中文描述： | DUAL, SERIAL INPUT LOADING, 2 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 4/12页 |
| 文件大小： | 319K |
| 代理商： | AD7242KR |
AD7242/AD7244
TIMING CHARACTERISTICS
1, 2
REV. A
–4–
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Limit at T
MIN
, T
MAX
(J, K, A, B Versions)
Limit at T
MIN
, T
MAX
(S Version)
Parameter
Units
Conditions/Comments
t
1
t
2
t
33
t
4
t
5
t
6
50
75
150
30
75
40
50
100
200
40
100
40
ns min
ns min
ns min
ns min
ns min
ns min
TFS
to TCLK Falling Edge
TCLK Falling Edge to
TFS
TCLK Cycle Time
Data Valid to TCLK Setup Time
Data Valid to TCLK Hold Time
LDAC
Pulse Width
NOTES
1
Timing specifications are sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-
age level of 1.6 V.
2
See Figure 6.
3
TCLK Mark/Space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
REF INA, REF INB to AGND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
J, K Versions
AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55
°
C to +125
°
C
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V)
PIN CONFIGURATIONS
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°
C
Power Dissipation (Any Package) to +75
°
C . . . . . . . 550 mW
Derates above +75
°
C by . . . . . . . . . . . . . . . . . . . . . 6 mW/
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIP
SOIC
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