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参数资料
| 型号： | AD7243AQ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | LC2MOS 12-Bit Serial DACPORT |
| 中文描述： | SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, CDIP16 |
| 封装： | CERDIP-16 |
| 文件页数： | 11/12页 |
| 文件大小： | 171K |
| 代理商： | AD7243AQ |
REV. A
–11–
AD7243
Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC
low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
When valid data has been loaded into all the registers, the
SYNC
input should be taken high and a common
LDAC
pulse
used to update all the DACs simultaneously.
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
1. Take the
SYNC
line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
3. Take the
SYNC
line high.
4. Pulse the
LDAC
line low. This updates all output channels
simultaneously on the falling edge of
LDAC
.
To reduce the number of opto-couplers, the
LDAC
line could
be driven from a one shot which is triggered by the rising edge
on the
SYNC
line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
V
OUT
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA OUT
CLOCK OUT
SYNC OUT
CONTROL OUT
CONTROLLER
V
DD
V
OUT
(A)
QUAD OPTO-COUPLER
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
OUT
(B)
V
OUT
(C)
V
OUT
(D)
V
OUT
V
OUT
V
OUT
Figure 17. Four-Channel Opto-lsolated Interface
相关PDF资料 |
PDF描述 |
|---|---|
| AD7243AR | LC2MOS 12-Bit Serial DACPORT |
| AD7243BN | 47 UF, 20V CAP., TANTALUM |
| AD7243BQ | LC2MOS 12-Bit Serial DACPORT |
| AD7243BR | SM IC/74HC08 SO-14 QUAD 2-IN |
| AD7243SQ2 | LC2MOS 12-Bit Serial DACPORT |
相关代理商/技术参数 |
参数描述 |
|---|---|
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| AD7243AR-REEL | 功能描述:IC DAC 12BIT W/AMP W/REF 16-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD7243ARZ | 功能描述:IC DAC 12BIT W/AMP W/REF 16-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD7243ARZ | 制造商:Analog Devices 功能描述:IC, DAC, 12BIT, 300KSPS, SOIC-16 |
| AD7243ARZ-REEL | 功能描述:IC SRL DAC 12BIT LC2MOS 16-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:DACPORT® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
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