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参数资料
| 型号： | AD7243BQ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | LC2MOS 12-Bit Serial DACPORT |
| 中文描述： | SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, CDIP16 |
| 封装： | CERDIP-16 |
| 文件页数： | 4/12页 |
| 文件大小： | 171K |
| 代理商： | AD7243BQ |
AD7243
–4–
REV. A
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
Pin
Mnemonic
Description
1
REFIN
Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
Clear, Logic Input. Taking this input low sets V
OUT
to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
Digital Ground. Ground reference for all digital circuitry.
Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
Analog Ground. Ground reference for all analog circuitry.
Output Offset Resistor for the amplifier. It is connected to V
OUT
for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
Positive Power Supply (+12 V to +15 V).
2
REFOUT
3
CLR
4
BIN
/COMP
5
6
7
SCLK
SDIN
SYNC
8
9
DGND
LDAC
10
DCEN
11
SDO
12
13
AGND
R
OFS
14
V
OUT
15
V
SS
16
V
DD
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at V
OUT
when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at V
OUT
when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
Digital Feedthrough
This is a measure of the voltage spike that appears on V
OUT
as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with
LDAC
held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (V
SS
) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
DAC CODE
0V
{
Figure 1. Effect of Negative Offset (Single Supply)
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